ics1893cy-10 Integrated Device Technology, ics1893cy-10 Datasheet - Page 119

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ics1893cy-10

Manufacturer Part Number
ics1893cy-10
Description
3.3-v 10base-t/100base-tx Integrated Phyceiver
Manufacturer
Integrated Device Technology
Datasheet

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9.5.2 Timing for Transmit Clock (TXCLK) Pins
ICS1893CY-10 Rev 1/07
TXCLK
Table 9-9
interfaces.
Table 9-9. Transmit Clock Timing
Figure 9-3. Transmit Clock Timing Diagram
Period
Time
t2a
t2b
t2c
t2d
t1
ICS1893CY-10 Data Sheet - Release
lists the significant time periods for signals on the Transmit Clock (TXCLK) pins for the various
TXCLK Duty Cycle
TXCLK Period
TXCLK Period
TXCLK Period
TXCLK Period
Figure 9-3
Parameter
shows the timing diagram for the time periods.
Copyright © 2007, Integrated Device Technology, Inc.
100M MII (100Base-TX)
10M MII (10Base-T)
100M Symbol Interface (100Base-TX)
10M Serial Interface (10Base-T)
All rights reserved.
t1
120
Conditions
t2x
Chapter 9 DC and AC Operating Conditions
Min.
35
Typ. Max. Units
400
100
50
40
40
65
ns
ns
ns
ns
%

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