mpc8569e Freescale Semiconductor, Inc, mpc8569e Datasheet - Page 39

• Manufacturer Part Number: mpc8569e
• Description: Mpc8569e Powerquicc Iii Integrated Processor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

The following figure shows the undershoot and overshoot voltages at the interfaces of the MPC8569E.
The core voltage must always be provided at nominal 1.0 or 1.1 V. See
to the processor interface I/Os is provided through separate sets of supply pins and must be provided at the voltages shown in
Table
are simple CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The DDR2 and DDR3 SDRAM interface
uses differential receivers referenced by the externally supplied Dn_MVREF signal (nominally set to GV
for the SSTL_1.8 electrical signaling standard for DDR2 or 1.5-V electrical signaling for DDR3. The DDR DQS receivers
cannot be operated in single-ended fashion. The complement signal must be properly driven and cannot be grounded.
Freescale Semiconductor
3. The input voltage threshold scales with respect to the associated I/O supply voltage. (B,M,L,O)V
V
IH
Nominal (B,G,L,O,X)V
Figure 7. Overshoot/Undershoot Voltage for BV
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
Note:
1. Note that t
(B,G,L,O,X)V
For I
For DDR, t
For eLBC, t
. F or eLBC, t
For SerDEs XV
V
IL
2
(B,G,L,O,X)V
C and JTAG, t
GND – 0.3 V
GND – 0.7 V
CLOCK
CLOCK
CLOCK
CLOCK
DD
DD
+ 20%
DD
refers to the clock period associated with the respective interface:
+ 5%
GND
references Dn_MCK.
, t
references LCLKn
references LCLKn
DD
CLOCK
CLOCK
references SYSCLK.
references SD_REF_CLK.
Not to Exceed 10%
Table 3
of t
DD
CLOCK
/GV
for actual recommended core voltage. Voltage
1
DD
/LV
Overall DC Electrical Characteristics
DD
/OV
DD
/XV
DD
DD
DD
/2) as is appropriate
based receivers
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