mpc8569e Freescale Semiconductor, Inc, mpc8569e Datasheet - Page 86

• Manufacturer Part Number: mpc8569e
• Description: Mpc8569e Powerquicc Iii Integrated Processor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

PCI Express
2.10.3
This section contains the DC specifications for the physical layer of PCI Express on this device.
2.10.3.1
This section discusses the PCI Express AC physical layer transmitter specifications for 2.5 Gb/s.
The following table defines the PCI Express (2.5Gb/s) AC specifications for the differential output at all transmitters (TXs). The
parameters are specified at the component pins. The AC timing specifications do not include RefClk jitter.
86
At recommended operating conditions with ScoreVDD = 1.0 V ± 3%. and 1.1 V ± 3%
At recommended operating conditions with XV
DC input
impedance
Powered down
DC input
impedance
Electrical idle
detect threshold
Notes:
1. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in
2. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM)
3. The RX DC common mode impedance that exists when no power is present or fundamental reset is asserted. This helps
Unit Interval
Minimum TX eye
width
Maximum time
between the jitter
median and
maximum
deviation from the
median
as the RX device when taking measurements. If the clocks to the RX and TX are not derived from the same reference clock,
the TX UI recovered from 3500 consecutive UI must be used as a reference for the eye diagram.
there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port.
ensure that the receiver detect circuit will not falsely assume a receiver is powered on when it is not. This term must be
measured at 300 mV above the RX ground.
Parameter
Parameter
Table 49. PCI Express (2.5 Gb/s) Differential Receiver (RX) Input DC Specifications (continued)
Table 50. PCI Express (2.5Gb/s) Differential Transmitter (TX) Output AC Specifications
PCI Express AC Physical Layer Specifications
PCI Express AC Physical Layer Transmitter Specifications
Z
Z
V
DIFFp-p
RX-DC
RX-HIGH-IMP-DC
RX-IDLE-DET-
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
UI
T
T
to-MAX-JITTER
TX-EYE
TX-EYE-MEDIAN-
Symbol
Symbol
Min
399.88 400.00 400.12
40
50
65
0.70
Min
DD
—
= 1.0 V ± 3%. and 1.1 V ± 3%
Typ
50
—
—
Typ
—
—
Max
175
60
—
Max
0.15
—
Unit
mV
ΚΩ
Ω
Unit
ps
UI
UI
Required RX D+ as well as D– DC impedance
(50 ± 20% tolerance). See Notes 1 and 2.
Required RX D+ as well as D– DC Impedance when
the receiver terminations do not have power. See Note
3.
V
Measured at the package pins of the receiver.
RX-IDLE-DET-DIFFp-p
Each UI is 400 ps ± 300 ppm. UI does not account
for spread spectrum clock dictated variations. See
Note 1.
The maximum transmitter jitter can be derived as
T
See Notes 2 and 3.
Jitter is defined as the measurement variation of the
crossing points (V
recovered TX UI. A recovered TX UI is calculated
over 3500 consecutive unit intervals of sample data.
Jitter is measured using all edges of the 250
consecutive UI in the center of the 3500 UI used for
calculating the TX UI. See Notes 2 and 3.
TX-MAX-JITTER
= 1 – T
TX-DIFFp-p
= 2 × |V
Comments
Comments
TX-EYE
Figure 46
Freescale Semiconductor
RX-D+
= 0 V) in relation to a
= 0.3 UI.
– V
RX-D–
must be used
|.