mpc8569e Freescale Semiconductor, Inc, mpc8569e Datasheet - Page 74

• Manufacturer Part Number: mpc8569e
• Description: Mpc8569e Powerquicc Iii Integrated Processor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

Ethernet Management Interface
2.7.1.1
The following table provides the MII management AC timing specifications.
74
At recommended operating conditions with LV
At recommended operating conditions with LV
Input low current (LV
Output high voltage (LV
Output low voltage (LV
Note:
1. The symbol V
MDC frequency
MDC period
MDC clock pulse width high
MDC to MDIO valid
MDC to MDIO delay
MDIO to MDC setup time
MDIO to MDC hold time
MDC rise time
MDC fall time
Notes:
1. The symbols used for timing specifications follow the pattern of t
2. This parameter is dependent on the platform clock frequency (MIIMCFG [MgmtClk] field determines the clock frequency of
3. This parameter is dependent on the platform clock frequency. The delay is equal to 16 platform clock periods ±3 ns. For
4. t
5. MDC to MDIO Data valid t
(Min setup = cycle time – max delay
inputs and t
data timing (MD) for the time t
Also, t
state (V) relative to the t
convention is used with the appropriate letter: R (rise) or F (fall).
the Mgmt Clock CE_MDC).
example, with a platform clock of 400 MHz, the min/max delay is 40 ns ± 3 ns.
plb_clk
MDDVKH
is the QUICC Engine block clock/2.
Parameter
(first two letters of functional block)(reference)(state)(signal)(state)
MII Management AC Electrical Specifications
IN
symbolizes management data timing (MD) with respect to the time data input signals (D) reaching the valid
, in this case, represents the LV
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
DD
Parameter
DD
Table 41. MII Management DC Electrical Characteristics (continued)
DD
= Max, V
= Min, I
MDC
= Min, I
MDKHDV
clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter
Table 42. MII Management AC Timing Specifications
MDC
IN
OL
OH
= 0.5 V)
= 4.0 mA)
is a function of clock period and max delay time (t
from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time.
= –4.0 mA)
Symbol
t
t
t
t
MDKHDV
MDKHDX
MDDVKH
MDDXKH
t
t
t
DD
DD
f
t
MDCH
MDCR
MDCF
MDC
MDC
= 3.3 V
= 3.3 V ± 5%.
1
IN
(16 × t
symbol referenced in
2× (t
plb_clk
Min
plb_clk
32
10
—
—
—
—
0
Symbol
V
V
I
OH
OL
IL
*8)
) – 3
(first two letters of functional block)(signal)(state)(reference)(state)
for outputs. For example, t
Table 2
–600
Typ
400
Min
2.5
2.4
—
—
—
—
—
—
—
—
and
Table
(16 × t
MDKHDX
Max
0.4
—
—
3.
MDKHDX
Max
plb_clk
10
10
—
—
—
—
—
—
).
) + 3
symbolizes management
Freescale Semiconductor
Unit
μA
V
V
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Notes
3, 4, 5
Notes
—
—
1
—
—
—
—
—
—
for
2
4