mpc8569e Freescale Semiconductor, Inc, mpc8569e Datasheet - Page 45

• Manufacturer Part Number: mpc8569e
• Description: Mpc8569e Powerquicc Iii Integrated Processor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

2.3.2
The real time clock timing (RTC) input is sampled by the core complex bus clock (CCB_clk). The output of the sampling latch
is then used as an input to the counters of the PIC and the time base unit of the e500; there is no need for jitter specification.
The minimum pulse width of the RTC signal must be greater than 2x the period of the CCB_clk. That is, minimum clock high
time is 2 × t
if not needed.
2.3.3
The following table provides the gigabit Ethernet reference clock (TX_CLK) AC timing specifications.
2.3.4
A description of the overall clocking of this device is available in the MPC8569E PowerQUICC III Integrated Host Processor
Family Reference Manual in the form of a clock subsystem block diagram. For information about the input clock requirements
of other functional blocks such as SerDes, Ethernet Management, eSDHC, and Enhanced Local Bus see the specific interface
section.
2.4
This section describes the DC and AC electrical specifications for the DDR2 and DDR3 SDRAM controller interface of the
MPC8569E. Note that the required GV
Freescale Semiconductor
At recommended operating conditions with LV
TX_CLK frequency
TX_CLK cycle time
TX_CLK rise and fall time
TX_CLK duty cycle
TX_CLK jitter
Notes:
1. Rise and fall times for TX_CLK are measured from 0.5 and 2.0 V for LV
2. TX_CLK is used to generate the GTX clock for the UEC transmitter with 2% degradation. The TX_CLK duty cycle can be
3. Gigabit transmit 125-MHz source. This signal must be generated externally with a crystal or oscillator, or is sometimes
4. For GMII and TBI modes, TX_CLK is provided to UCC1 through QE_PC[8:11,14,15] (CLK9-12,15,16) and to UCC2 through
5. System/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is
guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing
loosened from 47%/53% as long as the PHY device can tolerate the duty cycle generated by the UEC GTX_CLK. See
Section 2.6.3.7, “RGMII and RTBI AC Timing Specifications,”
provided by the PHY. TX_CLK is a 125-MHz input into the UCC Ethernet Controller and is used to generate all 125-MHz
related signals and clocks in the following modes: GMII, TBI, RTBI, RGMII.
QE_PC[2,3,6,7,15:17](CLK3,4,7,8,16:18). For RGMII and RTBI modes, TX_CLK is provided to UCC1 and UCC3 through
QE_PC11(CLK12) and to UCC2 and UCC4 through QE_PC16 (CLK17).
Parameter/Condition
CCB_clk
DDR2 and DDR3 SDRAM Controller
Real Time Clock Timing
Gigabit Ethernet Reference Clock Timing
Other Input Clocks
1000Base-T for RGMII, RTBI
, and minimum clock low time is 2 × t
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
LV
LV
DD
DD
GMII, TBI
Table 12. TX_CLK
= 2.5 V
= 3.3 V
DD
DD
(typ) is 1.8 V for DDR2 SDRAM and GV
= 2.5 V ± 125 mV / 3.3 V ± 165 mV.
t
G125R
t
G125H
Symbol
t
t
G125
G125
—
/t
/t
G125F
G125
CCB_clk
3,4
AC Timing Specifications
. There is no minimum RTC frequency; RTC may be grounded
for duty cycle for 10Base-T and 100Base-T reference clock.
Min
45
47
—
—
—
—
DD
= 2.5 V, and from 0.6 and 2.7 V for LV
Typical
125
—
—
—
8
DD
(typ) is 1.5 V for DDR3 SDRAM.
DDR2 and DDR3 SDRAM Controller
± 150
Max
0.75
1.0
55
53
—
—
MHz
Unit
ns
ns
ps
%
DD
= 3.3 V.
Notes
2, 5
1, 5
2, 5
—
—
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