mpc8569e Freescale Semiconductor, Inc, mpc8569e Datasheet - Page 91

• Manufacturer Part Number: mpc8569e
• Description: Mpc8569e Powerquicc Iii Integrated Processor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

2.11.3
This section explains the DC requirements for the Serial RapidIO interface.
2.11.3.1
The characteristics and DC requirements of the separate SerDes reference clocks of the SRIO interface are described in
Section 2.9.2.3, “DC Level Requirement for SerDes Reference Clocks.”
2.11.3.2
The LP-serial transmitter electrical and timing specifications are given in the following sections.
The differential return loss, S11, of the transmitter in each case are better than the following:
The reference impedance for the differential return loss measurements is 100-Ω resistive. Differential return loss includes
contributions from on-chip circuitry, chip packaging, and any off-chip components related to the driver. The output impedance
requirement applies to all valid output levels.
It is recommended that the 20%–80% rise/fall time of the transmitter, as measured at the transmitter output, in each case have
a minimum value 60 ps.
It is recommended that the timing skew at the output of an LP-serial transmitter between the two signals that comprise a
differential pair not exceed 25 ps at 1.25 GB, 20 ps at 2.50 GB, and 15 ps at 3.125 GB.
The following table defines the serial RapidIO transmitter DC specifications.
2.11.3.3
The LP-serial receiver electrical and timing specifications are given in the following sections.
Receiver input impedance shall result in a differential return loss better that 10 dB and a common mode return loss better than
6 dB from 100 MHz to (0.8) × (baud frequency). This includes contributions from on-chip circuitry, the chip package, and any
off-chip components related to the receiver. AC coupling components are included in this requirement. The reference impedance
for return loss measurements is 100-Ω resistive for differential return loss and 25-Ω resistive for common mode.
Freescale Semiconductor
At recommended operating conditions with XV
Output voltage
Long-run differential output voltage
Short-run differential output voltage
Note:
1. Voltage relative to COMMON of either signal comprising a differential pair.
•
•
–10 dB for (Baud Frequency) ÷ 10 < Freq(f) < 625 MHz
–10 dB + 10log(f ÷ 625 MHz) dB for 625 MHz ≤ Freq(f) ≤ Baud Frequency
Parameter
Table 52. SRIO Transmitter DC Timing Specifications—1.25, 2.5, and 3.125 GBauds
DC Requirements for Serial RapidIO
DC Requirements for Serial RapidIO SD_REF_CLK and SD_REF_CLK
DC Serial RapidIO Timing Transmitter Specifications
DC Serial RapidIO Receiver Specifications
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
DD
Symbol
V
V
DIFFPP
DIFFPP
= 1.0 V ± 3%. and 1.1 V ± 3%
V
O
–0.40
Min
800
500
Typ
—
—
—
1600
1000
Max
2.30
mV p-p
mV p-p
Unit
Serial RapidIO (SRIO)
V
Notes
—
—
1
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