mpc8569e Freescale Semiconductor, Inc, mpc8569e Datasheet - Page 51

• Manufacturer Part Number: mpc8569e
• Description: Mpc8569e Powerquicc Iii Integrated Processor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
At recommended operating conditions with GV
MDQ/MECC/MDM output setup with
respect to MDQS
MDQ/MECC/MDM output hold with
respect to MDQS
Notes:
1. The symbols used for timing specifications follow the pattern of t
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS.
4. Note that t
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
6. Parameters tested in DDR2 mode are to 400, 533, 667, and 800 MHz data rate and in DDR3 mode to 667 and 800 MHz data
7. DDR3 only
8. DDR2 only
inputs and t
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
t
(A) are setup (S) or output valid time. Also, t
(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). t
of the MDQS override bits (called WR_DATA_DELAY) in the TIMING_CFG_2 register. This will typically be set to the same
delay as in DDR_SDRAM_CLK_CNTL[CLK_ADJUST]. The timing parameters listed in the table assume that these 2
parameters have been set to the same adjustment value. See the MPC8569E PowerQUICC III Integrated Host Processor
Family Reference Manual for a description and understanding of the timing modifications enabled by use of these bits.
(MECC), or data mask (MDM). The data strobe must be centered inside of the data eye at the pins of the microprocessor.
rate.
DDKHAS
symbolizes DDR timing (DD) for the time t
DDKHMH
(first two letters of functional block)(reference)(state)(signal)(state)
Parameter
Table 20. DDR2 and DDR3 SDRAM Interface Output AC Timing Specifications
For the ADDR/CMD setup and hold specifications in
control register is set to adjust the memory clocks by ½ applied cycle.
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
follows the symbol conventions described in note 1. For example, t
800 MHz
667 MHz
533 MHz
400 MHz
800 MHz
667 MHz
533 MHz
400 MHz
DD
of 1.8 V ± 5% for DDR2 or 1.5 V ± 5% for DDR3.
Symbol
t
t
t
t
DDKLDX
DDKHDS,
DDKHDX,
DDKLDS
DDKLDX
MCK
1
symbolizes DDR timing (DD) for the time t
memory clock reference (K) goes from the high (H) state until outputs
NOTE
(first two letters of functional block)(signal)(state)(reference)(state)
280
320
400
450
280
320
400
450
Min
538
700
538
700
for outputs. Output hold time can be read as DDR timing
7
8
7
8
7
8
7
8
Table
20, it is assumed that the clock
DDKHMH
DDKHMH
DDR2 and DDR3 SDRAM Controller
Max
—
—
—
—
—
—
—
—
can be modified through control
describes the DDR timing (DD)
MCK
memory clock reference
Unit
6
ps
ps
Notes
for
5
5
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