mpc8569e Freescale Semiconductor, Inc, mpc8569e Datasheet - Page 81

• Manufacturer Part Number: mpc8569e
• Description: Mpc8569e Powerquicc Iii Integrated Processor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
•
SD_REF_CLK
SD_REF_CLK
SD_REF_CLK
SD_REF_CLK
— For external DC-coupled connection, as described in
— For external AC-coupled connection, there is no common mode voltage requirement for the clock driver. Since the
Single-ended mode
— The reference clock can also be single-ended. The SD_REF_CLK input amplitude (single-ended swing) must be
— The SD_REF_CLK input average voltage must be between 200 and 400 mV.
— To meet the input amplitude requirement, the reference clock inputs might need to be DC- or AC-coupled
Figure 40. Differential Reference Clock Input DC Requirements (External DC-Coupled)
Figure 41. Differential Reference Clock Input DC Requirements (External AC-Coupled)
Characteristics,”
mode voltage) to be between 100 and 400 mV. The following figure shows the SerDes reference clock input
requirement for DC-coupled connection scheme.
external AC-coupling capacitor blocks the DC level, the clock driver and the SerDes reference clock receiver
operate in different command mode voltages. The SerDes reference clock receiver in this connection scheme has
its common mode voltage set to SCOREGND. Each signal wire of the differential inputs is allowed to swing below
and above the command mode voltage (SCOREGND). The following figure shows the SerDes reference clock
input requirement for AC-coupled connection scheme.
between 400 and 800 mV peak-peak (from V
ground.
reference clock input requirement for single-ended signaling mode.
externally. For the best noise performance, the reference of the clock could be DC- or AC-coupled into the unused
phase (SD_REF_CLK) through the same source impedance as the clock input (SD_REF_CLK) in use.
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
200 mV < Input Amplitude or Differential Peak < 800 mV
200 mV < Input Amplitude or Differential Peak < 800 mV
the maximum average current requirements sets the requirement for average voltage (common
min
to V
Section 2.9.2.2, “SerDes Reference Clock Receiver
max
) with SD_REF_CLK either left unconnected or tied to
High-Speed SerDes Interfaces (HSSI)
Figure 42
100 mV < V
Vmin
Vmax
shows the SerDes
>
<
V
Vcm – 400 mV
Vcm + 400 mV
max
cm
V
< 800 mV
< 400 mV
min
Vcm
> 0 V
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