mpc8569e Freescale Semiconductor, Inc, mpc8569e Datasheet - Page 41

• Manufacturer Part Number: mpc8569e
• Description: Mpc8569e Powerquicc Iii Integrated Processor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

The following table provides the PLL lock times.
Freescale Semiconductor
Core PLL lock time
Platform PLL lock time
QUICC Engine block PLL lock time
DDR PLL lock times
Maximum rise/fall time of HRESET
Minimum assertion time for SRESET
PLL input setup time with stable SYSCLK before HRESET negation
Input setup time for POR configurations (other than PLL configuration)
with respect to negation of HRESET
Input hold time for all POR configurations (including PLL configuration)
with respect to negation of HRESET
Maximum valid-to-high impedance time for actively driven POR
configurations with respect to negation of HRESET
Note:
1. There may be some extra current leakage when driving signals high during this time.
2. Reset assertion timing requirements for DDR3 DRAMs may differ.
3. TRST is an asynchronous level sensitive signal. For guidance on how this requirement can be met, refer to the JTAG signal
4. SYSCLK is the primary clock input for the MPC8569E.
5. System/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is
termination guidelines in AN4232 MPC8569E PowerQUICC III Design Checklist.
guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
Table 5. RESET Initialization Timing Specifications (continued)
Parameter
Parameter
Table 6. PLL Lock Times
Min
—
—
3
2
4
8
Min
—
—
—
—
Overall DC Electrical Characteristics
Max
—
—
—
—
1
5
Max
100
100
100
100
SYSCLK
SYSCLK
SYSCLK
SYSCLK
SYSCLK
SYSCLK
Unit
Unit
Notes
μs
μs
μs
μs
—
5
4
4
4
4
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