pga370 ETC-unknow, pga370 Datasheet - Page 19

• Manufacturer Part Number: pga370
• Description: Mpu Pentium Iii 64-bit 0.18um 700mhz 370-pin Fcpga
• Manufacturer: ETC-unknow

2.4
2.4.1
2.5
Datasheet
Due to the large number of transistors and high internal clock speeds, the processor is capable of
generating large average current swings between low and full power states. The fluctuations can
cause voltages on power planes to sag below their nominal values if bulk decoupling is not
adequate. Care must be taken in the board design to ensure that the voltage provided to the
processor remains within the specifications listed in
violations (in the event of a voltage sag) or a reduced lifetime of the component (in the event of a
voltage overshoot). Unlike SC242 based designs, motherboards utilizing the PGA370 socket
must provide high frequency decoupling capacitors on all power planes for the processor.
Processor V
The regulator for the V
Table
specifications can result in timing violations (during V
component (during V
The processor requires both high frequency and bulk decoupling on the system motherboard for
proper AGTL+ (AGTL) bus operation. See the AGTL+ buffer specification in the
Intel
appropriate platform design guide for recommended capacitor component placement. The
minimum recommendation for the processor decoupling is listed below. All capacitors should be
placed within the PGA370 socket cavity and mounted on the primary side of the motherboard. The
capacitors are arranged to minimize the overall inductance between the V
pins.
For additional decoupling requirements, please refer to the appropriate platform design guide for
recommended capacitor component value, quantity and placement.
Processor System Bus Clock and Processor Clocking
The BCLK input directly controls the operating speed of the system bus interface. All AGTL+/
AGTL system bus timing parameters are specified with respect to the rising edge of the BCLK
input.
The Coppermine-T processor will implement an auto-detect mechanism that will let the processor
use either single-ended or differential signaling for the system bus and processor clocking. The
processor checks to see if the signal on pin Y33 is toggling. If this signal is toggling then the
processor operates in differential mode. Refer to
Resistor values and clock topology are listed in the appropriate platform design guide for a
differential implementation.
Decoupling Guidelines
1. V
2. V
3. V
®
7) while maintaining the required tolerances (also defined in
CC CORE
TT
REF
Pentium
decoupling - 0.1 µF capacitors in 0603 package.
decoupling - 0.1 µF and 0.001 µF capacitors in 0603 package placed near the V
decoupling - 4.7 µF capacitors in a 1206 package.
®
Pentium
II Processor Developer's Manual for more information. Also, refer to the
CC
CORE
CC CORE
CC CORE
®
and AGTL+ (AGTL) Decoupling
III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
overshoot).
input must be capable of delivering the dI
Figure 6
Table
CC CORE
for a differential clocking example.
7. Failure to do so can result in timing
sag) or a reduced lifetime of the
Table
7). Failure to meet these
CC CORE
CC CORE
/dt (defined in
and Vss power
REF
pins.
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