pga370 ETC-unknow, pga370 Datasheet - Page 37

• Manufacturer Part Number: pga370
• Description: Mpu Pentium Iii 64-bit 0.18um 700mhz 370-pin Fcpga
• Manufacturer: ETC-unknow

2.12
2.12.1
Datasheet
Table 14. System Bus AC Specifications (SET Clock)
System Bus AC Specifications
The processor system bus timings specified in this section are defined at the socket pins on the
bottom of the motherboard. Unless otherwise specified, timings are tested at the processor pins
during manufacturing. Timings at the processor pins are specified by design characterization. See
Section 7.0
Table 14
These specifications are placed into the following categories:
system bus clock specifications,
contains the CMOS signal group specifications,
Table 19
All processor system bus AC specifications for the AGTL+/AGTL signal group are relative to the
rising edge of the BCLK input. All AGTL+/AGTL timings are referenced to V
‘1’ logic levels unless otherwise specified.
The timings specified in this section should be used in conjunction with the I/O buffer models
provided by Intel. These I/O buffer models, which include package information, are available for
the Pentium III processor in the FC-PGA package in Viewlogic* XTK/XNS* model format
(formerly known as QUAD format) and IBIS * 3.1 format as the Pentium III Processor for the
PGA370 Socket I/O Buffer Models (Electronic Format).
AGTL and AGTL+ layout guidelines are also available in the appropriate platform design guide.
Care should be taken to read all notes associated with a particular timing parameter.
I/O Buffer Model
An electronic copy of the I/O Buffer Model for the AGTL+ and CMOS signals is available at
Intel’s Developer’s Website (http://developer.intel.com). The model is for use in single processor
designs and assumes the presence of motherboard R
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Pentium III processors at all frequencies.
2. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 1.25 V at the processor pin.
System Bus Frequency
T1: BCLK Period
T2: BCLK Period Stability
T3: BCLK High Time
T4: BCLK Low Time
T5: BCLK Rise Time
T6: BCLK Fall Time
All AGTL+ signal timings (address bus, data bus, etc.) are referenced at 1.00 V at the processor pins.
through
and covers APIC bus timing, and
for the processor signal definitions.
T# Parameter
Pentium
Table 20
®
list the AC specifications associated with the processor system bus.
III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
Table 16
10.0
Min
7.5
2.5
1.4
2.4
1.4
0.4
0.4
contains the AGTL+/AGTL specifications,
Table 20
100.00
133.33
Nom
Table 18
1, 2
TT
covers power on timing.
±250
±250
values as described in
Max
1.6
1.6
contains timings for the reset conditions,
Table 14
MHz
Unit
ns
ps
ns
ns
ns
ns
and
Figure
9
9
9
9
9
Table 15
Table 12 on page
REF
for both ‘0’ and
contain the
Table 17
4, 5, 10
6, 7, 10
4, 5, 11
6, 7, 11
Notes
9, 10
9, 11
9, 10
9, 11
3, 8
3, 8
4
36.
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