pga370 ETC-unknow, pga370 Datasheet - Page 23

• Manufacturer Part Number: pga370
• Description: Mpu Pentium Iii 64-bit 0.18um 700mhz 370-pin Fcpga
• Manufacturer: ETC-unknow

Datasheet
Table 3. System Bus Signal Groups
Table 4. System Bus Signal Groups (AGTL)
The groups and the signals contained within each group are shown in
Section 7.0
NOTES:
1. See
2. The BR0# pin is the only BREQ# signal that is bidirectional. See
3. These signals are specified for Vcc
4. These signals are 2.5 V tolerant.
5. V
6. RESET# must always be terminated to V
7. This signal is not supported by all processors. Refer to the Pentium
8. This signal is used to control the value of the processor on-die termination resistance. Refer to the platform
AGTL+ Input
AGTL+ Output
AGTL+ I/O
CMOS Input
CMOS Input
CMOS Output
System Bus
Clock
APIC Clock
APIC I/O
Power/Other
AGTL Input
AGTL Output
AGTL I/O
CMOS Input
CMOS Input
(1.8 V)
CMOS Output
internal BREQ# signals are mapped onto the BR[1:0]# pins after the agent ID is determined.
VID[3:0] is described in
V
V
V
BSEL[1:0] is described in
All other signals are described in
signal.
complete listing of processors that support this pin.
design guide for the recommended pull-down resistor value.
Group Name
Group Name
CC CORE
TT
SS
CC
4
1.5
is used to terminate the system bus and generate V
Section 7.0
is system ground.
,
3
9
V
CC
9
4
is the power supply for the processor core and is described in
for a description of these signals.
3
4
3
5
9
2.5
3
,
Pentium
Vcc
for information on the these signals.
CMOS
BPRI#, BR1#
PRDY#
A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#, BPM[1:0]#,
BR0#
A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SLP#, SMI#,
STPCLK#
PWRGOOD
FERR#, IERR#, THERMTRIP#
BCLK
PICCLK
PICD[1:0]
BSEL[1:0], CLKREF, CPUPRES#, EDGCTRL, PLL[2:1], RESET2#, SLEWCTRL,
THERMDN, THERMDP, RTTCTRL
V
BPRI#, BR1#
PRDY#
A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#, BPM[1:0]#,
BR0#
A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SLP#, SMI#,
STPCLK#
PWRGOOD
FERR#
CC CORE
Section
2
2
are described in
, D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, HIT#, HITM#, LOCK#, REQ[4:0]#, RP#
, D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, HIT#, HITM#, LOCK#, REQ[4:0]#, RP#,
Section 2.8.2
®
3
, IERR#
, V
III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
REF
2.6.
7
7
Section
, DEFER#, RESET#
, DEFER#, RESET#
1
, V
CMOS
3
, THERMTRIP#
SS
, V
and
(1.5 V for the Pentium III processor) operation.
TT
Section
7.0.
TT
1
on the motherboard, on-die termination is not provided for this
Section
, Reserved
(Sheet 1 of 2)
2.3.
3
7.0.
, VID[3:0]
6
8
6
, RSP#, TRDY#, RS[2:0]#
, V
,RESET2#, RS[2:0]#, RSP#, TRDY#
REF
CORE DET
Signals
Signals
on the motherboard.
13
, BSEL[1:0]
Section 7.0
, VID[3:0], V
®
III Processor Specification Update for a
Section
Table 3
13
for more information. The
CC 1.5
2.6.
,
and
V
CC 2.5
Table
,
V
CC CMOS
4. Refer to
,
23