pga370 ETC-unknow, pga370 Datasheet - Page 43

• Manufacturer Part Number: pga370
• Description: Mpu Pentium Iii 64-bit 0.18um 700mhz 370-pin Fcpga
• Manufacturer: ETC-unknow

Datasheet
Figure 12. System Bus Setup and Hold Timings
Figure 13. System Bus Reset and Configuration Timings
(A[14:5]#, BR0#,
BR1#, FLUSH#,
BCLK#
BCLK
V
Ts = T8, T12, T27 (Setup Time)
Th = T9, T13, T28 (Hold Time)
V = Vref for AGTL signal group; 0.75V for APIC and TAP signal groups
Configuration
Cross
RESET#
BCLK#
BCLK
= Crossing point of BLCK and BCLK#
INT#)
Pentium
T9 = (AGTL+ Input Hold Time)
T8 = (AGTL+ Input Setup Time)
T10 = (RESET# Pulse Width)
T16 = (Reset Configuration Signals (A[14:5]#, BR0#, BR1#, FLUSH#, INIT#) Setup Time)
T17 = (Reset Configuration Signals (A[14:5]#, BR0#, BR1#, FLUSH#, INIT#) Hold Time)
®
III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
V
Cross
Ts
V
Valid
Th
T10
NOTE: Single-Ended clock uses BCLK only,
Differential clock uses BCLK and BCLK#
NOTE: Single-Ended clock uses BCLK only,
Differential clock uses BCLK and BCLK#
T16
Valid
T9
T8
T17
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