pga370 ETC-unknow, pga370 Datasheet - Page 54

• Manufacturer Part Number: pga370
• Description: Mpu Pentium Iii 64-bit 0.18um 700mhz 370-pin Fcpga
• Manufacturer: ETC-unknow

Pentium
3.4
3.4.1
54
Figure 20. Non-AGTL+ (Non-AGTL) Overshoot/Undershoot, Settling Limit, and Ringback
Note: The undershoot guideline limits transitions exactly as described for the ATGL+/AGTL signals. See
®
III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
Non-AGTL+ (Non-AGTL) Signal Quality Specifications and
Measurement Guidelines
There are three signal quality parameters defined for non-AGTL+ signals: overshoot/undershoot,
ringback, and settling limit. All three signal quality parameters are shown in
AGTL+ signal group.
NOTES:
Overshoot/Undershoot Guidelines
Overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high
voltage or below V
signal edge rates (see
repeated overshoot events on 1.5 V or 2.5 V tolerant buffers if the charge is large enough (i.e., if
the overshoot is great enough). Permanent damage to the processor is the likely result of excessive
overshoot/undershoot. Violating the overshoot/undershoot guideline will also make satisfying the
ringback specification difficult. The overshoot/undershoot guideline is 0.3 V and assumes the
absence of diodes on the input. These guidelines should be verified in simulations without the on-
chip ESD protection diodes present because the diodes will begin clamping the 1.5 V and 2.5 V
tolerant signals beginning at approximately 0.7 V above the appropriate supply and 0.7 V below
V
rely on the diodes for overshoot/undershoot protection as this will negatively affect the life of the
components and make meeting the ringback specification very difficult.
Figure
1. V
SS
PICCLK, and PWRGOOD. BCLK and PICCLK signal quality is detailed in
. If signals are not reaching the clamping voltage, this will not be an issue. A system should not
HI
= 1.5 V for all non-AGTL+ signals except for BCLK, PICCLK, and PWRGOOD. V
18.
V
HI
V
V
LO
SS
SS
. The overshoot guideline limits transitions beyond V
Figure 20
Overshoot
Time
for non-AGTL+ signals). The processor can be damaged by
Settling Limit
Rising-Edge
Ringback
Undershoot
Section
Settling Limit
CC
3.1.
Figure 20
or V
HI
= 2.5 V for BCLK,
Falling-Edge
Ringback
SS
due to the fast
for the non-
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