pga370 ETC-unknow, pga370 Datasheet - Page 79

• Manufacturer Part Number: pga370
• Description: Mpu Pentium Iii 64-bit 0.18um 700mhz 370-pin Fcpga
• Manufacturer: ETC-unknow

Datasheet
NOTES:
10.Future low voltage AGTL PGA370 designs define these pins as GND. Refer to the appropriate platform
12.Future low voltage AGTL PGA370 designs will redefine these pins. Refer to the appropriate platform design
13.On AGTL and differential clock platforms, this pin is defined as BCLK#.
11. Future low voltage AGTL PGA370 designs define this pin as RESERVED and must be left unconnected.
1. These pins are required for backwards compatibility with other Intel processors. They are not used by the
2. RESET# signal must be connected to pins AH4 and X4 for backwards compatibility. Refer to the appropriate
3. VCC
4. These V
5. This pin is required for backwards compatibility. If backwards compatibility is not required, this pin may be left
6. Previously, PGA370 designs defined this pin as a GND. It is now reserved and must be left unconnected
7. Previously, PGA370 socket designs defined this pin as a GND. It is now CLKREF.
8. For Uniprocessor designs, this pin is not used and it is defined as RESERVED. Refer to the Pentium
9. Future low voltage AGTL PGA370 designs will redefine this pin as V
Pentium III processor. Refer to the appropriate platform design guide and
details.
platform design guide and
then RESET2# (X4) should be connected to GND.
066xh). For designs which do not support the Celeron processors (CPUID 066xh), and for compatibility with
future processors, these V
design guide and
connected to V
connected to V
(N/C).
processor Specification Update for a complete listing of processors that support DP operation.
design guide for connectivity and to the Pentium
processors that support the new pinout definition.
design guide for connectivity and to the Pentium
processors that support the new pinout definition.
Refer to the appropriate platform design guide for connectivity.
guide for connectivity and to the Pentium
processors that support the new pinout definition.
1.5
V must be supplied by the same voltage source supplying the V
TT
pins must be left unconnected (N/C) for backwards compatibility with Celeron processors (CPUID
Pentium
TT
CC CORE
.
Section 7.1
. Refer to the appropriate platform design guide for implementation details.
®
TT
Section 7.1
III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
pins should be connected to the V
for implementation details. For dual processor designs, these pins must be
for implementation details. If backwards compatibility is not required,
®
III processor Specification Update for a complete listing of
®
®
III processor Specification Update for a complete listing of
III processor Specification Update for a complete listing of
TT
plane. Refer to the appropriate platform
TT
. Refer to the appropriate platform
TT
Section 7.1
pins.
for implementation
®
III
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