pga370 ETC-unknow, pga370 Datasheet - Page 41

• Manufacturer Part Number: pga370
• Description: Mpu Pentium Iii 64-bit 0.18um 700mhz 370-pin Fcpga
• Manufacturer: ETC-unknow

Datasheet
Figure 9. Generic Clock Waveform
Note: For
1. All signals, during their invalid states, must be guarded against spurious levels from effecting the platform
2. Configuration Input signals include: A[14:5], BR0#, BR1#, INIT#. For timing of these signals, please refer to
1.
2. All AC timings for the AGTL+ signals at the processor pins are referenced to the BCLK rising
3. All AC timings for the APIC I/O signals at the processor pins are referenced to the PICCLK
4. All AC timings for the TAP signals at the processor pins are referenced to the TCK rising edge
during processor power-up sequence.
Table 17
Figure 9
B C L K #
Figure 9
edge at 1.25 V. All AGTL+ signal timings (address bus, data bus, etc.) are referenced at 1.00 V
at the processor pins.
rising edge at 1.25 V. All APIC I/O signal timings are referenced at 0.75 V at the processor
pins.
at 0.75 V. All TAP signal timings (TMS, TDI, etc.) are referenced at 0.75 V at the processor
pins.
B C L K
V c ro s s
and
through
through
Figure
Pentium
13.
Figure
Figure 15
T p = T 1 ( B C L K P e r io d )
®
III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
15, the following apply:
are to be used in conjunction with
T p
N O T E : S in g le - E n d e d c lo c k u s e s B C L K o n ly ,
D if f e r e n tia l c lo c k u s e s B L C K a n d B C L K #
Table 14
through
Table
V ih
V il
20.
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