pga370 ETC-unknow, pga370 Datasheet - Page 39

• Manufacturer Part Number: pga370
• Description: Mpu Pentium Iii 64-bit 0.18um 700mhz 370-pin Fcpga
• Manufacturer: ETC-unknow

Datasheet
Table 16. System Bus AC Specifications (AGTL+ or AGTL Signal Group)
NOTES:
10.This specification applies to the Pentium III processor running at 100 MHz system bus frequency.
12.BREQ signals at 133 MHz system bus observe a 1.2 ns minimum setup time.
13.For AGTL, V
11. This specification applies to the Pentium III processor running at 133 MHz system bus frequency.
1. Unless otherwise noted, all specifications in this table apply to Pentium III processors at all frequencies.
2. These specifications are tested during manufacturing.
3. All timings for the AGTL+ signals are referenced to the BCLK rising edge at 1.25 V at the processor pins (for
4. Valid delay timings for these signals are specified into 50
5. A minimum of 3 clocks must be guaranteed between two active-to-inactive transitions of TRDY#.
6. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously. For 2-way MP
7. Specification is for a minimum 0.40 V swing from V
8. Specification is for a maximum 1.0 V (2/3 V
9. This should be measured after V
T7: AGTL+ Output Valid Delay
T8: AGTL+ Input Setup Time
T9: AGTL+ Input Hold Time
T10: RESET# Pulse Width
AGTL, the timings are referenced to the rising edge of BCLK and the falling edge of BCLK# at the processor
pins). All AGTL+ signal timings (compatibility signals, etc.) are referenced at 1.00 V (2/3 V
processor pins.
R
with 56
systems, RESET# should be synchronous.
rate of 0.3V/ns.
rate of 3V/ns.
TT
. For AGTL platforms, the valid delay timings are specified into 50
T# Parameter
on-die R
REF
Pentium
is 2/3 V
TT
.
TT
®
±3%.
III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
CC CORE
0.40
1.20
0.95
1.00
1.00
Min
, V
TT
TT
, Vcc
for AGTL) swing from V
Max
3.25
CMOS
REF
- 200 mV to V
, and BCLK become stable.
to 1.5 V, V
Unit
ms
ns
ns
ns
ns
REF
REF
TT
- 1V to V
to 1.25 V, V
+ 200 mV. This assumes an edge
at 1.0 V ±2% and with 56
Figure
12
12
12
13
11
1, 2, 3, 13
TT
. This assumes an edge
REF
at 2/3 V
5, 6, 7, 11, 12
TT
5, 6, 7, 10
4, 10, 11
6, 9, 10
for AGTL) at the
Notes
8, 10
TT
±2% and
on-die
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