aduc7062 Analog Devices, Inc., aduc7062 Datasheet
aduc7062
Related parts for aduc7062
aduc7062 Summary of contents
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... LFCSP (5 mm × 5 mm) 48-lead LFCSP 48-lead LQFP Derivatives: 48-lead LQFP and 48-lead LFCSP, dual ADCs (ADuC7060); 32-lead LFCSP, dual ADCs (ADuC7061); 32-lead LFCSP, single ADC (ADuC7062) APPLICATIONS Industrial automation and process control Intelligent, precision sensing systems loop- based smart sensors ...
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... ADuC7060/ADuC7061/ADuC7062 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Functional Block Diagram .............................................................. 3 Specifications ..................................................................................... 4 Electrical Specifications ............................................................... 4 Timing Specifications .................................................................. 8 Absolute Maximum Ratings ............................................................ 9 ESD Caution .................................................................................. 9 Pin Configurations and Function Descriptions ......................... 10 Terminology .................................................................................... 14 Overview of the ARM7TDMI Core ............................................. 15 Thumb Mode (T) ........................................................................ 15 Multiplier (M) ............................................................................. 15 Embedded ICE (I) ...................................................................... 15 ARM Registers ............................................................................ 15 Interrupt Latency ...
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... W/U TIMER PWM PRECISION REFERENCE 14-BIT TEMP DAC SENSOR Figure 1. Rev. PrA | Page 3 of 100 ADuC7060/ADuC7061/ADuC7062 MEMORY 32kB FLASH RESET 4kB RAM XTAL1 ON-CHIP OSC (3%) XTAL2 PLL GPIO PORT UART PORT SPI PORT PORT VIC (VECTORED INTERRUPT CONTROLLER) ADuC7060/ ADuC7061/ ADuC7062 ...
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... ADuC7060/ADuC7061/ADuC7062 SPECIFICATIONS ELECTRICAL SPECIFICATIONS V = 2.5 V ± GND internal reference REF+ REF− chip precision oscillator, all specifications T Table 1. ADuC706x Specifications Parameter Test Conditions/Comments ADC SPECIFICATIONS 1 Conversion Rate Chop off, ADC normal operating mode Chop on, ADC normal operating mode ...
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... ADC , chop off 67 ADC 0.1 AGND chop on 75 ADC , chop off 67 ADC = 25°C −0.06 A −20 Rev. PrA | Page 5 of 100 ADuC7060/ADuC7061/ADuC7062 Typ Max V − 0.7 DD 1.2 600 300 150 75 37.5 18.75 9.375 0.5 113 AVDD − 0.1 AVDD 0 − 1.2 5.5 113 1.2 +0.06 ±10 ...
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... ADuC7060/ADuC7061/ADuC7062 Parameter Test Conditions/Comments External Reference Input Range Divide by 2 Initial Error REF DAC CHANNEL SPECIFICATIONS kΩ Voltage Range 12-BIT MODE 14 DC Specifications Resolution Relative Accuracy Differential Nonlinearity Guaranteed monotonic Offset Error 1.2 V internal reference Gain Error V REF AVDD range ...
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... Valid for primary ADC gain setting of PGA = 4 to 64. 3 Tested at gain range = 4 after initial offset calibration. 4 Measured with an internal short. A System zero-scale calibration will remove this error. 5 Measured with an internal short. 6 These numbers do not include internal reference temperature drift. ADuC7060/ADuC7061/ADuC7062 Min Typ 0.008 7.8 10,000 20 ±1 10 ...
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... ADuC7060/ADuC7061/ADuC7062 7 Factory calibrated at gain = 1. 8 System calibration at specific gain range removes the error at this gain range. 9 Measured using external reference. 10 Limited by minimum absolute input voltage range. 11 Valid for a differential input less than 10 mV. 12 Measured using the box method. 13 References up to AVDD are accommodated by setting ADC0CON Bit 12. ...
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... Lead Temperature, Soldering 260°C Reflow (15 sec) ADuC7060/ADuC7061/ADuC7062 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational + 0 ...
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... ADuC7060/ADuC7061/ADuC7062 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS P1.0/IRQ1/SIN/T0 ADC5/EXT_REF2IN− NOTES CONNECT. 2. THE LFCSP_VQ HAS AN EXPOSED PADDLE THAT MUST BE CONNECTED TO GND. Table 3. Pin Function Descriptions (48-Lead LQFP and 48-Lead LFCSP) 1 Type Pin No. Mnemonic 1 RESET I 2 TMS I 3 P1.0/IRQ1/SIN/T0 I/O 4 P1.1/SOUT I/O 5 P1.2/SYNC I/O 6 P1.3/TRIP ...
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... JTAG Reset. Input pin used for debug and download only. JTAG Data Out. Output pin used for debug and download only. JTAG Data In. Input pin used for debug and download only. JTAG Clock Pin. Input pin used for debug and download only. Rev. PrA | Page 11 of 100 ADuC7060/ADuC7061/ADuC7062 ...
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... ADuC7060/ADuC7061/ADuC7062 P1.0/IRQ1/SIN/T0 ADC5/EXT_REF2IN− ADC4/EXT_REF2IN+ NOTES CONNECT. 2. THE LFCSP_VQ HAS AN EXPOSED PADDLE THAT MUST BE CONNECTED TO GND. Table 4. Pin Function Descriptions ADuC7061/ADuC7062 32-Lead LFCSP Pin No. Mnemonic Type 1 RESET I 2 TMS I 3 P1.0/IRQ1/SIN/T0 I/O 4 P1.1/SOUT I/O 5 DAC0 O 6 ADC5/EXT_REF2IN− ADC4/EXT_REF2IN ADC3 ...
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... JTAG Reset. Input pin used for debug and download only. JTAG Data Out. Output pin used for debug and download only. JTAG Data In. Input pin used for debug and download only. JTAG Clock. Input pin used for debug and download only. Rev. PrA | Page 13 of 100 ADuC7060/ADuC7061/ADuC7062 ...
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... ADuC7060/ADuC7061/ADuC7062 TERMINOLOGY Conversion Rate The conversion rate specifies the rate at which an output result is available from the ADC, once the ADC has settled. The sigma-delta (Σ-Δ) conversion techniques used on this part mean that while the ADC front-end signal is over sampled at a relatively high sample rate, a subsequent digital filter is used to decimate the output giving a valid 24-bit data conversion result at output rates from kHz ...
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... Once in a debug state, the processor registers can be interrogated, as can the Flash/EE, SRAM, and memory mapped registers. ADuC7060/ADuC7061/ADuC7062 ARM7 Exceptions The ARM7 supports five types of exceptions, with a privileged processing mode associated with each type. The five types of exceptions are as follows: Normal interrupt or IRQ ...
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... ADuC7060/ADuC7061/ADuC7062 such necessary to ensure that the stack does not overflow. This is dependent on the performance of the compiler that is used. When an exception occurs, some of the standard registers are replaced with registers specific to the exception mode. All exception modes have replacement banked registers for the stack pointer (R13) and the link register (R14) as represented in Figure 4 ...
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... Read/write access Function: This 8-bit register allows user code to remap either RAM or Flash/EE space into the bottom of the ARM memory space starting at Address 0x00000000. ADuC7060/ADuC7061/ADuC7062 Table 7. REMAP MMR Bit Designations Bit Description Reserved. These bits are reserved and should be written user code ...
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... ADuC7060/ADuC7061/ADuC7062 Table 8. FEEMOD MMR Bit Designations Bit Description 15:9 Reserved. 8 Reserved. Always set this bit to 0. 7:5 Reserved. Always set these bits to 0 except when writing keys. 4 Flash/EE Interrupt Enable. Set by user to enable the Flash/EE interrupt. The interrupt occurs when a command is complete. Cleared by user to disable the Flash/EE interrupt. ...
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... MMR. It requires a software key (see Table 10). Name: FEEPRO Address: 0xFFFF081C Default value: 0x00000000 Access: Read/write ADuC7060/ADuC7061/ADuC7062 FEEHIDE Register FEEHIDE MMR provides immediate protection. It does not require any software key. Note that the protection settings in FEEHIDE are cleared by a reset (see Table 10). Name: FEEHIDE Address: 0xFFFF0820 ...
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... ADuC7060/ADuC7061/ADuC7062 MEMORY MAPPED REGISTERS The memory mapped register (MMR) space is mapped into the upper two pages of the memory array, and accessed by indirect addressing through the ARM7 banked registers. The MMR space provides an interface between the CPU and all on-chip peripherals. All registers, except the core registers, reside in the MMR area ...
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... Indicates the priority level of an FIQ that has just caused an FIQ exception. Default Value Description 0x00 REMAP Control Register. See the Remap Operation section. 0x01 RSTSTA Status MMR. See the Reset section. 0x00 RSTCLR MMR for clearing RSTSTA register. Rev. PrA | Page 21 of 100 ADuC7060/ADuC7061/ADuC7062 ...
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... ADuC7060/ADuC7061/ADuC7062 Table 13. Timer Address Base = 0xFFFF0300 Access Address Name Byte Type 0x0320 T0LD 4 RW 0x0324 T0VAL 4 R 0x0328 T0CON 4 RW 0x032C T0CLRI 1 W 0x0330 T0CAP 4 R 0x0340 T1LD 4 RW 0x0344 T1VAL 4 R 0x0348 T1CON 2 RW 0x034C T1CLRI 1 W 0x0360 T2LD 2 RW ...
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... UART Standard Baud Rate Generator Divisor Value 0. 0x00 UART Interrupt Enable MMR 0. 0x00 UART Standard Baud Rate Generator Divisor Value 1. 0x01 UART Interrupt Identification 0. 0x03 UART Control Register 0. 0x00 UART Control Register 1. 0x60 UART Status Register 0. 0x0000 UART Fractional Divider MMR. Rev. PrA | Page 23 of 100 ADuC7060/ADuC7061/ADuC7062 ...
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... ADuC7060/ADuC7061/ADuC7062 2 Table 18 Base Address = 0XFFFF0900 Access Address Name Byte Type 0x0900 I2CMCON 2 R/W 0x0904 I2CMSTA 2 R 0x0908 I2CMRX 1 R 0x090C I2CMTX 1 W 0x0910 I2CMCNT0 2 R/W 0x0914 I2CMCNT1 1 R 0x0918 I2CADR0 1 R/W 0x091C I2CADR1 1 R/W 0x0924 I2CDIV 2 R/W 0x0928 I2CSCON 2 R/W 0x092C I2CSSTA 2 R/W 0x0930 I2CSRX 1 R/W 0x0934 I2CSTX ...
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... Compare Register 1 for PWM Output 4 and PWM Output 5. 0x0000 Compare Register 2 for PWM Output 4 and PWM Output 5. 0x0000 Frequency Control for PWM Output 4 and PWM Output 5. 0x0000 PWM Interrupt Clear Register. Writing any value to this register clears a PWM interrupt source. Rev. PrA | Page 25 of 100 ADuC7060/ADuC7061/ADuC7062 ...
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... ADuC7060/ADuC7061/ADuC7062 RESET There are four kinds of reset: external reset, power-on-reset, watchdog reset, and software reset. The RSTSTA register indicates the source of the last reset and can be written by user code to initiate a software reset event. The bits in this register can be cleared writing to the RSTCLR MMR at 0xFFFF0234 ...
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... TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Rev. PrA | Page 27 of 100 ADuC7060/ADuC7061/ADuC7062 //Set core to max CPU //speed of 10.24 MHz IRQ0 to IRQ3 Start-Up/Power-On Time TBD TBD TBD ...
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... ADuC7060/ADuC7061/ADuC7062 Power and Clock Control Registers Name: POWKEY1 Address: 0xFFFF0404 Default Value: 0xXXXX Access: Write Function: When writing to POWCON0, the value 0x01 must be written to this register in the instruction immediately before writing to POWCON0 Table 27. POWCON0 MMR Bit Designations Bit Name Description 7 Reserved This bit must always be set to 0 ...
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... Default Value: 0xXXXX Access: Write Function: When writing to PLLCON, the value 0x55 must be written to this register in the instruction immediately after writing to PLLCON. ADuC7060/ADuC7061/ADuC7062 Description These bits must always be set to 0. Oscillator Selection bits: [00] = Internal 32,768 Hz Oscillator [01] = Internal 32,768 Hz Oscillator [10] = External Crystal [11] = Internal 32,768 Hz Oscillator Rev ...
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... ADuC7060/ADuC7061/ADuC7062 ADC CIRCUIT INFORMATION INTERNAL REFERENCE IEXC0 IEXC1 AIN0 AIN1 CHOP MUX AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 GND_SW 50Ω AGND TEMPERATURE The ADuC706x incorporates two independent multichannel Σ-Δ ADCs. The primary ADC is a 24-bit, 5-channel ADC. The auxiliary ADC is a 16-bit Σ ...
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... The diagnostic current sources for the primary ADC analog inputs are controlled by the ADC0DIAG[1:0] bits in the ADC0CON register. Similarly, the diagnostic current sources for the auxiliary ADC analog inputs are controlled by the ADC1DIAG[1:0] bits in the ADC0CON register. Rev. PrA | Page 31 of 100 ADuC7060/ADuC7061/ADuC7062 ±75 mV ±150 mV ±300 mV ±600 mV (16) (8) ...
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... ADuC7060/ADuC7061/ADuC7062 Table 31. Example Scenarios for Using Diagnostic Current Sources Diagnostic Test Normal Result ADC0DIAG[1: Convert Expected differential result ADC0/ADC1 as normal with across ADC0/ADC1. diagnostic currents disabled. Enable 50 μA diagnostic current Main ADC changes by source on ADC0 by setting ΔV = +50 μA × R1. For example, ADC0DIAG[1: Convert ~100 mV for kΩ ...
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... ADC conversion result even though the ready bits have not been cleared. ADC Status Register Name: ADCSTA Address: 0xFFFF0500 Default value: 0x0000 Access: Read only Function: This read-only register holds general status information related to the mode of operation or current status of the ADuC7060/ADuC7061/ ADuC7062 ADCs. Rev. PrA | Page 33 of 100 ...
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... ADuC7060/ADuC7061/ADuC7062 Bit Name Description 4 ADC0THEX Primary Channel ADC Comparator Threshold. This bit is only valid if the primary channel ADC comparator is enabled via the ADCCFG MMR. This bit is set by hardware if the absolute value of the primary ADC conversion result exceeds the value written in the ADC0TH MMR. If the ADC threshold counter is used (ADC0TCL), this bit is only set when the specified number of primary ADC conversions equals the value in the ADC0THV MMR ...
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... ADC system full-scale calibration. In this mode, a full-scale calibration is performed on enabled ADC channels against an external full-scale voltage driven at the ADC input pins. The ADCxGN register is updated after a full-scale calibration sequence. ADuC7060/ADuC7061/ADuC7062 . RDY must be cleared to enable new data to be written to ADC0DAT/ADC1DAT ADC ...
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... ADuC7060/ADuC7061/ADuC7062 Primary ADC Control Register Name: ADC0CON Address: 0xFFFF050C Default value: 0x0000 Access: Read/write Function: The primary channel ADC control MMR is a 16-bit register. Note: If the primary ADC is reconfigured via ADC0CON, the auxiliary ADC is also reset. ADC0CON MMR Bit Designations Bit ...
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... ADC2/ADC5 (Single-Ended mode). [0101] = ADC3/ADC5 (Single-Ended mode). [0110] = ADC4/ADC5 (Single-Ended mode). [0111] = ADC6/ADC5 (Single-Ended mode). [1000] = ADC7/ADC5 (Single-Ended mode). [1001] = ADC8/ADC5 (Single-Ended mode). [1010] = ADC9/ADC5 (Single-Ended mode). [1011] = Internal Temp Sensor+/ Internal Temp Sensor− ADuC7060/ADuC7061/ADuC7062 Rev. PrA | Page 37 of 100 ...
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... ADuC7060/ADuC7061/ADuC7062 Bit Name Description [1100] = VREF+, VREF−. Note: This is the reference selected by the ADC1REF bits. [1101] = DAC_OUT/AGND. [1110] = Undefined. [1111] = Internal short to ADC3. TBC ADC1REF[2:0] Auxiliary Channel ADC Reference Select. [0 00] = Internal Reference selected. In ADC low power mode, the voltage reference selection is controlled by ADCMODE[5]. [0 01] = External reference inputs (VREF+, VREF− ...
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... Range Yes Yes Yes Rev. PrA | Page 39 of 100 ADuC7060/ADuC7061/ADuC7062 calculations should be divided ADC 1 t SETTLING 3 , 072 × ADC 4 , 072 f × ADC 1 131 , 072 f × × ...
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... ADuC7060/ADuC7061/ADuC7062 ADC Configuration Register Name: ADCCFG Address: 0xFFFF0518 Default Value: 0x00 Access: Read/write Function: The 8-bit ADC configuration MMR controls extended functionality related to the on-chip ADCs. Table 39. ADCCFG MMR Bit Designations Bit Name Description 7 GNDSW_EN Analog Ground Switch Enable. This bit is set user software to connect the external GND_SW pin to an internal analog ground reference point ...
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... ADC is in idle mode. An ADC must be enabled and in idle mode before being written to any offset or gain register. The ADC must be in idle mode for at least 23 μs. Table 42. ADC0OF MMR Bit Designations Bits Description ADC0 16-bit calibration offset value. ADuC7060/ADuC7061/ADuC7062 Rev. PrA | Page 41 of 100 ...
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... ADuC7060/ADuC7061/ADuC7062 Auxiliary Channel ADC Offset Calibration Register Name: ADC1OF Address: 0xFFFF0528 Default Value: Part specific, factory programmed Access: Read/write access Function: This offset MMR holds a 16-bit offset calibration coefficient for auxiliary channel. The register is configured at power- on with a factory default value. However, this register is automatically overwritten if an offset calibration of the auxiliary channel is initiated by the user via bits in the ADCMDE MMR ...
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... The result counter is enabled via ADCCFG[0]. This MMR is also reset to 0 when the Primary-ADC is reconfigured, that is, when the ADC0CON or ADCMDE are written. Table 47. ADCORCV MMR Bit Designations Bits Description ADC0 Result Counter register. ADuC7060/ADuC7061/ADuC7062 Rev. PrA | Page 43 of 100 ...
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... ADuC7060/ADuC7061/ADuC7062 Primary Channel ADC Threshold Register Name: ADCOTHRESH Address: 0xFFFF053C Default Value: 0x0000 Access: Read/write Function: This 16-bit MMR sets the threshold against which the absolute value of the Primary ADC conversion result is compared. In Unipolar mode ADC0TH[15:0] are compared, and in twos complement mode, ADC0TH[14:0] are compared ...
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... Figure 11. Primary ADC Accumulator/Comparator/Counter Block Diagram INTERRUPT (ADC0OR) FAST OVERRANGE 16 ADC0ACC ACCUMULATOR f ADC ADC (READABLE) ADC0ATH |ABSVAL| INTERRUPT ≥ ≥ (ADC*RDY) f ADC ADC0TH Rev. PrA | Page 45 of 100 ADuC7060/ADuC7061/ADuC7062 (READABLE) 32 INTERRUPT ≥ (ADC0ATHEX) ADC0THCNT UP/DOWN OPTION: UP/RESET INTERRUPT ≥ (ADC0THEX) ADC0THC ...
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... ADuC7060/ADuC7061/ADuC7062 Table 53. ADCOTHCNT MMR Bit Designations Bits Description ADC0 8-bit threshold counter limit register Primary Channel ADC Threshold Count Register Name: ADCOTHVAL Address: 0xFFFF0544 Default value: 0x00 Access: Read only Function: This 8-bit MMR increments every time the absolute value of a primary ADC conversion result attains |Result| ≥ ...
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... This 32-bit MMR holds the threshold value for the primary channel accumulator comparator. When the accumulator value in ADC0ACC exceeds the value in ADC0ATH, the ADC0ATHEX bit, ADCSTA, is set causing an interrupt if the corresponding bit in ADCMSKI is also enabled. Table 56. ADCOATH MMR Bit Designations Bits Description ADC0 32-bit accumulator comparator threshold register. ADuC7060/ADuC7061/ADuC7062 Rev. PrA | Page 47 of 100 ...
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... ADuC7060/ADuC7061/ADuC7062 Excitation Current Sources Control Register Name: IEXCON Address: 0xFFFF0570 Default Value: 0x00 Access: Read/write Function: This 8-bit MMR controls the two excitation current sources, IEXC0 and IEXC1. Table 57. IEXCON MMR Bit Designations Bits Name Description 7 IEXC1_EN Enable bit for IEXC1 current source. ...
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... REFIN– GND Figure 13. Example of a Thermocouple Interface Circuit ADuC7060/ ADuC7061/ ADuC7062 IEXC1 AIN0 RTD UART GPIO AIN1 REFIN+ REFIN– Figure 14. Example of an RTD Interface Circuit Rev. PrA | Page 49 of 100 ADuC7060/ADuC7061/ADuC7062 +2.5V SPI +2.5V VDD SPI ETC. GND ...
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... ADuC7060/ADuC7061/ADuC7062 DAC PERIPHERALS DAC The ADuC706x incorporates a 12-bit voltage output DAC on- chip. The DAC has a rail-to-rail voltage output buffer capable of driving 5 kΩ/100 pF. The DAC has four selectable ranges: • VREF (internal band gap 1.2 V reference) • VREF− to VREF+ • ...
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... Figure 15. The dotted line in Figure 15 indicates the ideal transfer function, and the solid line represents what the transfer function may look like with endpoint nonlinearities due to saturation of the output amplifier. Note that Figure 15 represents a transfer function in ADuC7060/ADuC7061/ADuC7062 0-to-AV mode only. In 0-to-V DD modes (with V lower nonlinearity is similar ...
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... ADuC7060/ADuC7061/ADuC7062 NONVOLATILE FLASH/EE MEMORY The ADuC706x incorporates Flash/EE memory technology on-chip to provide the user with nonvolatile, in-circuit reprogram- mable memory space. Like EEPROM, flash memory can be programmed in-system at a byte level, although it must first be erased. The erase is performed in page blocks result, flash memory is often, and more correctly referred to as Flash/EE memory ...
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... XIRQ2 (GPIO IRQ2 ) External Interrupt 2 19 XIRQ3 (GPIO IRQ3) External Interrupt 3 ADuC7060/ADuC7061/ADuC7062 IRQ The IRQ is the exception signal to enter the IRQ mode of the processor. It services general-purpose interrupt handling of internal and external events. All 32 bits are logically OR’ create a single IRQ signal to the ARM7TDMI core ...
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... ADuC7060/ADuC7061/ADuC7062 IRQCLR Register Name: IRQCLR Address: 0xFFFF000C Default value: 0x00000000 Access: Write only IRQSTA IRQSTA is a read-only register that provides the current enabled IRQ source status (effectively a logic AND of the IRQSIG and IRQEN bits). When set to 1, that source generates an active IRQ request to the ARM7TDMI core. There is no priority encoder or interrupt vector generation ...
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... IRQ/FIQ interrupts can be nested up to eight levels depending on the priority settings. An FIQ still has a higher priority than an IRQ. There fore, if the VIC is ADuC7060/ADuC7061/ADuC7062 enabled for both the FIQ and IRQ and prioritization is maximized, then it is possible to have 16 separate interrupt levels. ...
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... ADuC7060/ADuC7061/ADuC7062 Priority Registers The IRQ interrupt vector register, IRQVEC points to a memory address containing a pointer to the interrupt service routine of the currently active IRQ. This register should only be read when an IRQ occurs and IRQ interrupt nesting has been enabled by setting Bit 0 of the IRQCONN register. ...
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... Setting this bit to 1 enables nesting of FIQ interrupts. Clearing this bit, means no nesting or prioritization of FIQs is allowed. ADuC7060/ADuC7061/ADuC7062 FIQVEC Register The FIQ interrupt vector register, FIQVEC points to a memory address containing a pointer to the interrupt service routine of the currently active FIQ. This register should only be read when an FIQ occurs and FIQ interrupt nesting has been enabled by setting Bit 1 of the IRQCONN register ...
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... ADuC7060/ADuC7061/ADuC7062 External Interrupts (IRQ0 to IRQ3) The ADuC706x provides up to four external interrupt sources. These external interrupts can be individually configured as level or rising/falling edge triggered. To enable the external interrupt source, first of all, the appropriate bit must be set in the FIQEN or IRQEN register. To select the required edge or level to trigger on, the IRQCONE register must be appropriately configured ...
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... Preliminary Technical Data IRQCLRE Register Name: IRQCLRE Address: 0xFFFF0038 Default value: 0x00000000 Access: Read and write ADuC7060/ADuC7061/ADuC7062 Table 72. IRQCLRE MMR Bit Designations Bit Name Description 31:20 Reserved These bits are reserved and should not be written to. 19 IRQ3CLRI A 1 must be written to this bit in the IRQ3 interrupt service routine to clear an edge triggered IRQ3 interrupt ...
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... ADuC7060/ADuC7061/ADuC7062 TIMERS The ADuC706x features four general-purpose timer/counters. • Timer0 • Timer1 or wake-up timer • Timer2 or watchdog timer • Timer3 The four timers in their normal mode of operation can either be free running or periodic. In free running mode, the counter decrements/increments from the maximum or minimum value until zero/full scale and starts again at the maximum or minimum value ...
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... OR 32768 UP/DOWN COUNTER TIMER1 VALUE CAPTURE IRQ[31:0] Figure 18. Timer0 Block Diagram Rev. PrA | Page 61 of 100 ADuC7060/ADuC7061/ADuC7062 T0LD 0xFFFF0320 0x00000000 Read/write T0LD is a 32-bit register that holds the 32-bit value that is loaded into the counter. T0CLRI 0xFFFF032C Write only ...
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... ADuC7060/ADuC7061/ADuC7062 Timer0 Capture Register Name: T0CAP Address: 0xFFFF0330 Default value: 0x00000000 Access: Read only Function: This 32-bit register holds the 32-bit value captured by an enabled IRQ event. Timer0 Control Register Name: T0CON Address: 0xFFFF0328 Default value: 0x01000000 Access: Read/write Function: This 32-bit MMR configures the mode of operation of Timer0. ...
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... T1LD and T1VAL are 32-bit registers and hold 32-bit unsigned integers. T1VAL is read only. T1CLRI is an 8-bit register. Writing any value to this register clears the Timer1 interrupt. T1CON is the configuration MMR described in Table 75. ADuC7060/ADuC7061/ADuC7062 Timer1 Load Registers Name: T1LD Address: 0xFFFF0340 ...
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... ADuC7060/ADuC7061/ADuC7062 32.768kHz OSCILLATOR CORE CLOCK FREQUENCY/CD EXTERNAL 32.768kHz WATCH CRYSTAL Timer1 Control Register Name: T1CON Address: 0xFFFF0348 Default value: 0x0000 Access: Read/write Function: This 16-bit MMR configures the mode of operation of Timer1. Table 75. T1CON MMR Bit Designations Bit Name Description Reserved. ...
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... ARM7 core. By default, Timer2 continues to count during power-down. To disable this, set Bit 0 in T2CON recommended to use the default value, that is, that the watchdog timer continues to count during power-down. 32.768kHz ADuC7060/ADuC7061/ADuC7062 Timer2 Interface The Timer2 interface consists of four MMRs. • T2CON is the configuration MMR described in (Table TBD). • ...
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... ADuC7060/ADuC7061/ADuC7062 Timer2 Control Register Name: T2CON Address: 0xFFFF0368 Default value: 0x0000 Access: Read/write Function: The 16-bit MMR configures the mode of operation of Timer2 as is described in detail in Table 76. Table 76 T2CON MMR Bit Designations Bit Name Description Reserved. These bits are reserved and should be written user code. ...
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... Timer3 Clear Register Name: T3CLRI Address: 0xFFFF038C Access: Write only Function: This 8-bit, write only MMR is written (with any value) by user code to clear the interrupt. ADuC7060/ADuC7061/ADuC7062 Timer3 Value Register Name: T3VAL Address: 0xFFFF0384 Default value: 0xFFFF Access: Read only Function: T3VAL is a 16-bit register that holds the current value of Timer3 ...
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... ADuC7060/ADuC7061/ADuC7062 Table 77. T3CON MMR Bit Designations Bit Name Description Reserved. 17 T3CAPEN Event Enable Bit. Set by user to enable time capture of an event. Cleared by user to disable time capture of an event T3CAPSEL Event Select Range 31. The events are described in (Table TBD). ...
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... PWM2LEN Frequency Control for PWM Output 4 and PWM Output 5. PWMICLR PWM interrupt clear. ADuC7060/ADuC7061/ADuC7062 In all modes, the PWMxCOMx MMRs controls the point at which the PWM outputs change state. An example of the first pair of PWM outputs (PWM0 and PWM1) is shown in Figure 21. HIGH SIDE ...
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... ADuC7060/ADuC7061/ADuC7062 Table 79. PWMCON MMR Bit Designations Bit Name Description 14 SYNC Enables PWM Synchronization. Set the user so that all PWM counters are reset on the next clock edge after the detection of a high-to-low transition on the SYNC pin. Cleared by user to ignore transitions on the SYNC pin. ...
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... PWM1COM0 0xFFFF0F94 PWM1COM1 0xFFFF0F98 PWM1COM2 0xFFFF0F9C PWM2COM0 0xFFFF0FA4 PWM2COM1 0xFFFF0FA8 PWM2COM2 0xFFFF0FAC ADuC7060/ADuC7061/ADuC7062 MMR. Note that when using the PWM trip interrupt, the PWM interrupt should be cleared before exiting the ISR. This prevents generation of multiple interrupts. DIR PWM0 PWM1 ...
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... ADuC7060/ADuC7061/ADuC7062 PWM0COM0 Compare Register Name: PWM0COM0 Address: 0xFFFFF84 Default 0x00 value: Access: Read/write Function: PWM0 output pin goes high when the PWM timer reaches the count value stored in this register. PWM0COM1 Compare Register Name: PWM0COM1 Address: 0xFFFFF88 Default 0x00 value: Access: ...
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... Name: PWM2COM2 Address: 0xFFFFFAC Default 0x00 value: Access: Read/write Function: PWM5 output pin goes low when the PWM timer reaches the count value stored in this register. ADuC7060/ADuC7061/ADuC7062 PWM1LEN Register Name: PWM2LEN Address: 0xFFFFFB0 Default 0x00 value: Access: Read/write Function: PWM5 output pin goes high when the PWM timer reaches the value stored in this register ...
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... ADuC7060/ADuC7061/ADuC7062 UART SERIAL INTERFACE The ADuC7060 features a 16450-compatible UART. The UART is a full-duplex, universal, asynchronous receiver/transmitter. A UART performs serial-to-parallel conversion on data charac- ters received from a peripheral device, and parallel-to-serial conversion on data characters received from the ARM7TDMI. The UART features a fractional divider that facilitates high accuracy baud rate generation and a network addressable mode ...
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... Name: COMDIV0 Address: 0xFFFF0700 Default value: 0x00 Access: Read/write ADuC7060/ADuC7061/ADuC7062 UART Divisor Latch Register 1 This 8-bit register contains the most significant byte of the divisor latch that controls the baud rate at which the UART operates. Name: COMDIV1 Address: 0xFFFF0704 Default value: ...
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... ADuC7060/ADuC7061/ADuC7062 Table 84. COMCON0 MMR Bit Designations Bit Name 7 DLAB 6 BRK EPS 3 PEN 2 STOP WLS Description Divisor Latch Access. Set by user to enable access to COMDIV0 and COMDIV1 registers. Cleared by user to disable access to COMDIV0 and COMDIV1 and enable access to COMRX, COMTX, and COMIEN0. ...
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... Set automatically if data are overwritten before being read. Cleared automatically. Data Ready. Set automatically when COMRX is full. Cleared by reading COMRX. Rev. PrA | Page 77 of 100 ADuC7060/ADuC7061/ADuC7062 Name Description Reserved bits. Not used. LOOPBACK Loopback. Set by user to enable loopback mode. In loopback mode, the TxD is forced high ...
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... ADuC7060/ADuC7061/ADuC7062 UART Interrupt Enable Register 0 Name: COMIEN0 Address: 0xFFFF0704 Default value: 0x00 Access: Read/write Function: The 8-bit register enables and disables the individual UART interrupt sources. Table 87. COMIEN0 MMR Bit Designations Bit Name Description Reserved. Not used. 3 EDSSI Modem Status Interrupt Enable Bit. ...
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... GP0CON1. The following code example shows this in detail alternative function for P0.1 and P0 functionality for P0.1 and P0.3 Rev. PrA | Page 79 of 100 ADuC7060/ADuC7061/ADuC7062 2 C master mode, the ADuC7060 supports continuous C hardware testing. In loopback mode data signal. To configure 2 C mode. ...
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... ADuC7060/ADuC7061/ADuC7062 SERIAL CLOCK GENERATION 2 The I C master in the system generates the serial clock for a transfer. The master channel can be configured to operate in fast mode (400 kHz) or standard mode (100 kHz). The bit rate is defined in the I2CDIV MMR as follows UCLK f SERIAL CLOCK + + + ...
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... Set this bit to allow the device to compete for control of the bus even if another device is currently driving a Start Condition. Clear this bit to back off until the I2CMEN I C Master Enable bit. Set by user to enable I Cleared disable bus becomes free master mode master mode. Rev. PrA | Page 81 of 100 ADuC7060/ADuC7061/ADuC7062 ...
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... ADuC7060/ADuC7061/ADuC7062 Master Status Register Name: I2CMSTA Address: 0xFFFF0904 Default value: 0x0000 Access: Read Function: This 16-bit MMR is I Table 91 I2CMSTA MMR Bit Designations Bit Name Description Reserved. These bits are reserved I2CBBUSY I C Bus Busy Status Bit. This bit is set to 1 when a start condition is detected on the I This bit is cleared when a stop condition is detected on the bus ...
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... Name 7:1 I2CADR 0 Table 94. I2CADR0 MMR in 10-Bit Address Mode Bit Name 7:3 2:1 I2CMADR 0 Rev. PrA | Page 83 of 100 ADuC7060/ADuC7061/ADuC7062 I2CMCNT1 0xFFFF0914 0x00 Read This 8-bit MMR holds the number of bytes received so far during a read sequence with a slave device. I2CADR0 0xFFFF0918 0x00 Read/write This 8-bit MMR holds the 7-bit slave address + the read/write bit when the master begins communicating with a slave ...
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... ADuC7060/ADuC7061/ADuC7062 Address 1 Register Name: I2CADR1 Address: 0xFFFF091C Default value: 0x00 Access: Read/write Function: This 8-bit MMR is used in 10-bit addressing mode only. This register contains the least significant byte of the address. Table 95. I2CADR1 MMR in 10-Bit Address Mode Bit Name Description 7:0 I2CLADR These bits contain ADDR[7:0] in 10-bit addressing mode ...
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... C Slave Enable Bit. Set by user to enable I Clear to disable peripheral in slave mode General Call section for further details General Call section for further details general call commands. 2 Cslave mode slave mode. Rev. PrA | Page 85 of 100 ADuC7060/ADuC7061/ADuC7062 2 C bus. ...
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... ADuC7060/ADuC7061/ADuC7062 Slave Status Register Name: I2CSSTA Address: 0xFFFF092C Default value: 0x0000 Access: Read/write Function: This 16-bit MMR is the I Table 98. I2CSSTA MMR Bit Designations Bit Name Description 15 Reserved bit. 14 I2CSTA This bit is set Start Condition followed by a matching address is detected. ...
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... If the I2CSETEN bit in I2CSCON is =0, this bit goes high of the slave Tx FIFO is empty. If the I2CSETEN bit in I2CSCON is =1, this bit goes high just after the positive edge of SCL during the Write bit transmission. This bit asserts once only for a transfer. This bit is cleared after being read. ADuC7060/ADuC7061/ADuC7062 Rev. PrA | Page 87 of 100 ...
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... ADuC7060/ADuC7061/ADuC7062 Slave Receive Register Name: I2CSRX Address: 0xFFFF0930 Default value: 0x00 Access: Read Function: This 8-bit MMR is the Slave Transmit Register Name: I2CSTX Address: 0xFFFF0934 Default value: 0x00 Access: Write Function: This 8-bit MMR is the I register Hardware General Call Recognition Register ...
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... GP0CON0 = BIT0 + BIT1 + BIT2 + BIT3; GP0KEY1 = 0x7; GP0CON1 &=~ BIT1; GP0KEY2 = 0x13; ADuC7060/ADuC7061/ADuC7062 In slave mode, the SPICON register must be configured with the phase and polarity of the expected input clock. The slave accepts data from an external master up to 5.12 Mb. In both master and slave modes, data are transmitted on one edge of the SCL signal and sampled on the other ...
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... ADuC7060/ADuC7061/ADuC7062 SPI REGISTERS The following MMR registers control the SPI interface: SPISTA, SPIRX, SPITX, SPIDIV, and SPICON. SPI Status Register Name: SPISTA Address: 0xFFFF0A00 Default value: 0x00000000 Access: Read/write Function: This 32-bit MMR contains the status of the SPI interface in both master and slave modes. ...
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... ADuC7060/ADuC7061/ADuC7062 SPIRX Register Name: SPIRX Address: 0xFFFF0A04 Default value: 0x00 Access: Read Function: This 8-bit MMR is the SPI receive register. SPITX Register Name: SPITX Address: 0xFFFF0A08 Default value: 0x00 Access: Write Function: This 8-bit MMR is the SPI transmit register. Preliminary Technical Data ...
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... ADuC7060/ADuC7061/ADuC7062 Table 101. SPICON MMR Bit Designations Bit Name Description SPIMDE SPI IRQ mode bits. These bits configure when the Tx/Rx interrupts occur in a transfer. [00 interrupt occurs when 1 byte has been transferred. Rx interrupt occurs when 1 or more bytes have been received into the FIFO ...
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... Preliminary Technical Data Bit Name Description 1 SPIMEN Master Mode Enable Bit. Set by user to enable master mode. Cleared by user to enable slave mode. 0 SPIEN SPI Enable Bit. Set by user to enable the SPI. Cleared by user to disable the SPI. ADuC7060/ADuC7061/ADuC7062 Rev. PrA | Page 93 of 100 ...
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... ADuC7060/ADuC7061/ADuC7062 GENERAL-PURPOSE I/O The ADuC706x features up to sixteen general-purpose bidirectional input/output (GPIO) pins. In general, many of the GPIO pins have multiple functions that are configurable by user code. By default, the GPIO pins are configured in GPIO mode. All GPIO pins have an internal pull-up resistor with a drive capability of 1 ...
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... GPxDAT MMR. Cleared user; does not affect the data output. 15:0 Reserved. ADuC7060/ADuC7061/ADuC7062 GPxPAR REGISTERS The GPxPAR registers program the parameters for Port 0 and Port 1. Note that the GPxDAT MMR must always be written after changing the GPxPAR MMR. ...
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... Note that the analog and digital ground pins on the ADuC7060/ ADuC7061/ADuC7062 must be referenced to the same system ground reference point at all times. Finally, note that once the DVDD supply reaches 1 must ramp to 2. less than 128 ms. This is a requirement of the internal power-on-reset circuitry ...
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... MAX 0.02 NOM COPLANARITY 0.50 BSC 0.08 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 26. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ × Body, Very Thin Quad (CP-48-3) Dimensions shown in millimeters Rev. PrA | Page 97 of 100 ADuC7060/ADuC7061/ADuC7062 0.60 MAX PIN 1 INDICATOR EXPOSED 3.65 PAD 3.50 SQ (BOTTOM VIEW) 3 ...
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... SEATING 0.05 PLANE VIEW A ROTATED 90° CCW ORDERING GUIDE Model Temperature Range 1 ADuC7060BCPZ32 −40°C to +125°C 1 ADuC7060BSTZ32 −40°C to +125°C 1 ADuC7061BCPZ32 −40°C to +125°C ADuC7062BCPZ32 1 −40°C to +125° RoHS Compliant Part. 9.20 9.00 SQ 0.75 1.60 8.80 0.60 MAX 0. PIN 1 TOP VIEW 0.20 (PINS DOWN) 0.09 7° ...
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... ADuC7060/ADuC7061/ADuC7062 NOTES Preliminary Technical Data Rev. PrA | Page 99 of 100 ...
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... ADuC7060/ADuC7061/ADuC7062 NOTES ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR07079-0-6/08(PrA) Preliminary Technical Data Rev. PrA | Page 100 of 100 ...