aduc7062 Analog Devices, Inc., aduc7062 Datasheet - Page 55

• Manufacturer Part Number: aduc7062
• Description: Low-power, Precision Analog Microcontroller, Dual ?-? Adcs, Flash/ee, Arm7tdmi
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
Programmed Interrupts
Because the programmed interrupts are not maskable, they are
controlled by another register (SWICFG) that writes into both
IRQSTA and IRQSIG registers and/or the FIQSTA and FIQSIG
registers at the same time.
The 32-bit register dedicated to software interrupt is SWICFG
described in Table 61. This MMR allows the control of a
programmed source interrupt.
Table 61. SWICFG MMR Bit Designations
Bit
31 to 3
2
1
0
Any interrupt signal must be active for at least the minimum
interrupt latency time, to be detected by the interrupt controller
and to be detected by the user in the IRQSTA/FIQSTA register.
Vectored Interrupt Controller (VIC)
The ADuC7060 incorporates an enhanced interrupt control
system or vectored interrupt controller. The vectored interrupt
controller for IRQ interrupt sources is enabled by setting Bit 0
of the IRQCONN register. Similarly, Bit 1 of IRQCONN enables
the vectored interrupt controller for the FIQ interrupt sources.
The vectored interrupt controller provides the following
enhancements to the standard IRQ/FIQ interrupts:
•
•
Vectored Interrupts. This allows a user to define separate
interrupt service routine addresses for every interrupt
source. This is achieved by using the IRQBASE and
IRQVEC registers.
IRQ/FIQ interrupts can be nested up to eight levels
depending on the priority settings. An FIQ still has a
higher priority than an IRQ. There fore, if the VIC is
Description
Reserved.
Programmed Interrupt FIQ. Setting/clearing this bit
corresponds to setting/clearing Bit 1 of FIQSTA and
FIQSIG.
Programmed Interrupt IRQ. Setting/clearing this bit
corresponds to setting/clearing Bit 1 of IRQSTA and
IRQSIG.
Reserved.
Figure 17. Interrupt Structure
Rev. PrA | Page 55 of 100
•
VIC MMRs
IRQBASE Register
The vector base register, IRQBASE, is used to point to the start
address of memory used to store 32 pointer addresses. These
pointer addresses are the addresses of the individual interrupt
service routines.
Name:
Address:
Default value:
Access:
Table 62. IRQBASE MMR Bit Designations
Bit
31:16
15:0
IRQVEC Register
The IRQ interrupt vector register, IRQVEC points to a memory
address containing a pointer to the interrupt service routine of
the currently active IRQ. This register should only be read when
an IRQ occurs and IRQ interrupt nesting has been enabled by
setting Bit 0 of the IRQCONN register.
Name:
Address:
Default value:
Access:
Table 63. IRQVEC MMR Bit Designations
Bit
31:23
22:7
6:2
1:0
enabled for both the FIQ and IRQ and prioritization is
maximized, then it is possible to have 16 separate interrupt
levels.
Programmable Interrupt Priorities. Using the IRQP0 to
IRQP2 registers, an interrupt source can be assigned an
interrupt priority level value between 1 and 8.
Type
Read
only
R/W
Reserved
Type
Read only
R/W
ADuC7060/ADuC7061/ADuC7062
IRQBASE
0xFFFF0014
0x00000000
Read and write
IRQVEC
0xFFFF001C
0x00000000
Read only
Initial
value
0
0
0
0
Initial value
Reserved
0
Description
Always read as 0.
IRQBASE register value
Highest PriorityIRQ source. This
will be a value between 0 to 19
representing the possible interrupt
sources. For example, if the highest
currently active IRQ is Timer 1,
then these bits are [01000]
Reserved bits.
Always read as 0.
Vector Base address
Description