aduc7062 Analog Devices, Inc., aduc7062 Datasheet - Page 36

• Manufacturer Part Number: aduc7062
• Description: Low-power, Precision Analog Microcontroller, Dual ?-? Adcs, Flash/ee, Arm7tdmi
• Manufacturer: Analog Devices, Inc.

ADuC7060/ADuC7061/ADuC7062
Primary ADC Control Register
Name:
Address:
Default value:
Access:
Function:
Note:
ADC0CON MMR Bit Designations
Bit
15
14, 13
12
11
10
9 to 6
5, 4
Name
ADC0EN
ADCODIAG[1:0]
HIGHEXTREF0
AMP_CM
ADC0CODE
ADC0CH[3:0]
ADC0REF[1:0]
ADC0CON
0xFFFF050C
0x0000
Read/write
The primary channel ADC control MMR is a 16-bit register.
If the primary ADC is reconfigured via ADC0CON, the auxiliary ADC is also reset.
Primary Channel ADC Enable.
This bit must be set high if the external reference for ADC0 exceeds 1.35 V.
Primary Channel ADC Output Coding.
Primary Channel ADC Input Select.
Primary Channel ADC Reference Select.
Description
This bit is set to 1 by user code to enable the primary ADC.
Clearing this bit to 0 powers down the primary ADC and resets the respective ADC ready bit in the ADCSTA MMR
to 0.
Diagnostic Current Source Enable Bits.
0, 0 = current sources off.
0, 1 = enables 50 μA current source on selected positive input (for example, ADC0).
1, 0 = enables 50 μ A current source on selected negative input (for example, ADC1).
1, 1 = enables 50 μ A current source on both selected inputs (for example, ADC0 and ADC1).
Clear this bit when using the internal reference or an external reference of less than 1.35 V.
This bit is set to 1 by user to set the PGA output common-mode voltage to AVDD/2
This bit is cleared to 0 by user code to set the PGA output common-mode voltage to the PGA input common-
mode voltage level
This bit is set to 1 by user code to configure primary ADC output coding as unipolar.
This bit is cleared to 0 by user code to configure primary ADC output coding as twos complement.
[0000] = ADC0/ADC1 (differential mode).
[0001] = ADC0/ADC5 (single-ended mode).
[0010] = ADC1/ADC5 (single-ended mode).
[0011] = VREF+, VREF−. Note: This is the reference selected by the ADC0REF bits.
[0100] = Not Used. This bit combination is reserved for future functionality and should not be written.
[0101] = ADC2/ADC3 (differential mode).
[0110] = ADC2/ADC5 (single-ended mode).
[0111] = ADC3/ADC5 (single-ended mode).
[1000] = internal short to ADC0
[1001] = internal short to ADC1
1, 0 = VREF/136, 0 V, diagnostic, test voltage for gain settings ≤ 128. Note: If (REG_AVDD, AGND) divided-by-two
reference is selected, REG_AVDD is used for VREF in this mode. This leads to ADC0DAT scaled by two.
0, 0 = internal reference selected. In ADC low power mode, the voltage reference selection is controlled by
ADCMODE[5].
0, 1 = external reference inputs (VREF+, VREF−) selected. Set the HIGHEXTREF0 bit if reference voltage exceeds
1.3 V.
1, 0 = auxiliary external reference inputs (ADC4/EXT_REF2IN+, ADC5/EXT_REF2IN−) selected. Set the
HIGHEXTREF0 bit if the reference voltage exceeds 1.3 V.
1, 1 = (AVDD, AGND) divided-by-two selected. TBC
Rev. PrA | Page 36 of 100
Preliminary Technical Data