aduc7062 Analog Devices, Inc., aduc7062 Datasheet - Page 70

• Manufacturer Part Number: aduc7062
• Description: Low-power, Precision Analog Microcontroller, Dual ?-? Adcs, Flash/ee, Arm7tdmi
• Manufacturer: Analog Devices, Inc.

ADuC7060/ADuC7061/ADuC7062
Table 79. PWMCON MMR Bit Designations
Bit
14
13
12
11
10
9
8:6
5
4
3
2
1
0
1
In H-bridge mode, HMODE = 1. See Table 80 to determine the PWM outputs.
Name
SYNC
PWM5INV
PWM3NV
PWM1INV
PWMTRIP
ENA
PWMCP[2:0]
POINV
HOFF
LCOMP
DIR
HMODE
PWMEN
Enables PWM Synchronization.
If HOFF = 0 and HMODE = 1. Note: If not in H-Bridge mode, this bit has no effect.
PWM Clock Prescaler Bits. Sets UCLK divider.
Load Compare Registers.
Direction Control.
Set to 1 by the user to enable all PWM outputs.
Description
Set to 1 by the user so that all PWM counters are reset on the next clock edge after the detection of a high-to-low
transition on the SYNC pin.
Cleared by user to ignore transitions on the SYNC pin.
Set to 1 by the user to invert PWM5.
Cleared by user to use PWM5 in normal mode.
Set to 1 by the user to invert PWM3.
Cleared by user to use PWM3 in normal mode.
Set to 1 by the user to invert PWM1.
Cleared by user to use PWM1 in normal mode.
Set to 1 by the user to enable PWM trip interrupt. When the PWMTRIP input is low, the PWMEN bit is cleared and an
interrupt is generated.
Cleared by user to disable the PWMTRIP interrupt.
Set to 1 by the user to enable PWM outputs.
Cleared by user to disable PWM outputs.
If HOFF = 1 and HMODE = 1, see (Table TBD).
[000] = UCLK/2.
[001] = UCLK/4.
[010] = UCLK/8.
[011] = UCLK/16.
[100] = UCLK/32.
[101] = UCLK/64.
[110] = UCLK/128.
[111] = UCLK/256.
Set to 1 by the user to invert all PWM outputs.
Cleared by user to use PWM outputs as normal.
High Side Off.
Set to 1 by the user to force PWM0 and PWM2 outputs high. This also forces PWM1 and PWM3 low.
Cleared by user to use the PWM outputs as normal.
Set to 1 by the user to load the internal compare registers with the values in PWMxCOMx on the next transition of
the PWM timer from 0x00 to 0x01.
Cleared by user to use the values previously stored in the internal compare registers.
Set to 1 by the user to enable PWM0 and PWM1 as the output signals while PWM2 and PWM3 are held low.
Cleared by user to enable PWM2 and PWM3 as the output signals while PWM0 and PWM1 are held low.
Enables H-Bridge Mode.
Set to 1 by the user to enable H-Bridge mode and Bit 1 to Bit 5 of PWMCON.
Cleared by user to operate the PWMs in standard mode.
Cleared by user to disable all PWM outputs.
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Rev. PrA | Page 70 of 100
Preliminary Technical Data