aduc7062 Analog Devices, Inc., aduc7062 Datasheet - Page 82

• Manufacturer Part Number: aduc7062
• Description: Low-power, Precision Analog Microcontroller, Dual ?-? Adcs, Flash/ee, Arm7tdmi
• Manufacturer: Analog Devices, Inc.

ADuC7060/ADuC7061/ADuC7062
I
Name:
Address:
Default value:
Access:
Function:
Table 91 I2CMSTA MMR Bit Designations
Bit
15 to 11
10
9
8
7
6
5
4
3
2
1 to 0
2
C Master Status Register
Name
I2CBBUSY
I2CMRxFO
I2CMTC
I2CMNA
I2CMBUSY
I2CAL
I2CMNA
I2CMRXQ
I2CMTXQ
I2CMTFSTA
I2CMSTA
0xFFFF0904
0x0000
Read
This 16-bit MMR is I
Description
Reserved. These bits are reserved.
I
This bit is set to 1 when a start condition is detected on the I
This bit is cleared when a stop condition is detected on the bus.
Master Rx FIFO Overflow.
This bit is set to 1 when a byte is written to the Rx FIFO when it is already full.
This bit is cleared in all other conditions.
I
This bit is set to 1 when a transmission is complete between the master and the slave it was communicating with.
If the I2CMCENI bit in I2CMCON is set, an interrupt is generated when this bit is set.
Clear this interrupt source.
I
This bit is set to 1 when a no acknowledge (NACK). condition is received by the master in response to a data write
transfer.
If the I2CNACKENI bit in I2CMCON is set, an interrupt is generated when this bit is set.
This bit is cleared in all other conditions.
I
Set to 1 when the master is busy processing a transaction.
Cleared if the master is ready or if another master device has control of the bus.
I
This bit is set to 1 when the I
If the I2CALENI bit in I2CMCON is set, an interrupt is generated when this bit is set.
This bit is cleared in all other conditions.
I
This bit is set to 1 when a no acknowledge condition is received by the master in response to an Address.
If the I2CNACKENI bit in I2CMCON is set, an interrupt is generated when this bit is set.
This bit clears in all other conditions.
I
This bit is set to 1 when data enters the Rx FIFO. If the I2CMRENI in I2CMCON is set, an interrupt is generated.
This bit is cleared in all other conditions.
I
This bit goes high if the Tx FIFO is empty or only contains 1byte and the master has transmitted an
Address + write. If the I2CMTENI bit in I2CMCON is set, an interrupt is generated when this bit is set.
This bit is cleared in all other conditions.
I
00 = I
01 = 1 byte in Master Tx FIFO
10 = 1 byte in Master Tx FIFO
11 = I
2
2
2
2
2
2
2
2
2
C Bus Busy Status Bit.
C Transmission Complete Status Bit.
C Master No Acknowledge (NACK). Data Bit
C Master Busy Status Bit.
C Arbitration Lost Status Bit.
C Master No Acknowledge Address Bit.
C Master Receive Request Bit.
C Master Transmit Request bit.
C Master Tx FIFO Status Bits.
2
2
C Master Tx FIFO empty
C Master Tx FIFO Ffull.
2
C status register in master mode.
2
C master has lost in trying to gain control of the I
Rev. PrA | Page 82 of 100
2
C bus.
Preliminary Technical Data
2
C bus.