aduc7062 Analog Devices, Inc., aduc7062 Datasheet - Page 28

• Manufacturer Part Number: aduc7062
• Description: Low-power, Precision Analog Microcontroller, Dual ?-? Adcs, Flash/ee, Arm7tdmi
• Manufacturer: Analog Devices, Inc.

ADuC7060/ADuC7061/ADuC7062
Power and Clock Control Registers
Name:
Address:
Default Value:
Access:
Function:
Table 27. POWCON0 MMR Bit Designations
Bit
7
6
5
4
3
2 to 0
Name
Reserved
XPD
PLLPD
PPD
COREPD
CD[2:0]
POWKEY1
0xFFFF0404
0xXXXX
Write
When writing to POWCON0, the value 0x01
must be written to this register in the
instruction immediately before writing to
POWCON0
Description
This bit must always be set to 0.
XTAL Power Down.
Cleared by the user to power-down the external crystal circuitry.
Set by the user to enable the external crystal circuitry.
PLL Power Down. Timer peripherals power down if driven from the PLL output clock.
Timers driven from an active clock source remain in normal power mode.
This bit is cleared to 0 to power-down the PLL.
The PLL cannot be powered down if either the core or peripherals are enabled:
Bit 3, Bit 4, and Bit 5 must be cleared simultaneously.
Set by default, and set by hardware on a wake-up event.
Peripherals Power Down. The peripherals that are powered down by this bit are as follows:
SRAM, Flash/EE memory and GPIO interfaces, and SPI/I
Cleared to power-down the peripherals. The peripherals cannot be powered down if the core is enabled:
Bit 3 and Bit 4 must be cleared simultaneously.
Set by default, and/or by hardware, on a wake-up event. Wake-up timer (Timer1) can still be active
Core Power Down. If user code powers down the MCU, include a dummy MCU cycle after the power-down
command is written to POWCON.
Cleared to power-down the ARM core.
Set by default and set by hardware on a wake-up event.
Core clock depends on CD setting:
[000] = 10.24 MHz
[001] = 5.12 MHz
[010] = 2.56 MHz
[011] = 1.28 MHz [default value]
[100] = 640 kHz
[101] = 320 kHz
[110] = 160 kHz
[111] = 80 kHz
Rev. PrA | Page 28 of 100
Name:
Address:
Default Value:
Access:
Function:
2
C and UART serial ports.
POWCON0
0xFFFF0408
0x7B
Read/write
This register controls the clock divide bits
controlling the CPU clock (HCLK)
Preliminary Technical Data