aduc7062 Analog Devices, Inc., aduc7062 Datasheet - Page 89

• Manufacturer Part Number: aduc7062
• Description: Low-power, Precision Analog Microcontroller, Dual ?-? Adcs, Flash/ee, Arm7tdmi
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
SERIAL PERIPHERAL INTERFACE
The ADuc7060 integrates a complete hardware serial peripheral
interface (SPI) on-chip. SPI is an industry standard, synchronous
serial interface that allows eight bits of data to be synchronously
transmitted and simultaneously received, that is, full duplex up
to a maximum bit rate of 5.12 Mb.
The SPI port can be configured for master or slave operation
and typically consists of four pins: MISO, MOSI, SCL, and SS .
MISO (MASTER IN, SLAVE OUT) PIN
The MISO pin is configured as an input line in master mode
and an output line in slave mode. The MISO line on the master
(data in) should be connected to the MISO line in the slave
device (data out). The data is transferred as byte wide (8-bit)
serial data, MSB first.
MOSI (MASTER OUT, SLAVE IN) PIN
The MOSI pin is configured as an output line in master mode
and an input line in slave mode. The MOSI line on the master
(data out) should be connected to the MOSI line in the slave
device (data in). The data is transferred as byte wide (8-bit)
serial data, MSB first.
SCL (SERIAL CLOCK I/O) PIN
The master serial clock (SCL) synchronizes the data being
transmitted and received through the MOSI SCL period.
Therefore, a byte is transmitted/received after eight SCL
periods. The SCL pin is configured as an output in master mode
and as an input in slave mode.
In master mode, polarity and phase of the clock are controlled
by the SPICON register, and the bit rate is defined in the
SPIDIV register as follows:
The maximum speed of the SPI clock is independent on the
clock divider bits.
GP0CON0 = BIT0 + BIT1 + BIT2 + BIT3;
GP0KEY1 = 0x7;
GP0CON1 &=~ BIT1;
GP0KEY2 = 0x13;
f
SERIAL
CLOCK
=
2
×
1 (
+
f
UCLK
SPIDIV
)
// Select SPI/I
//Write to GP0KEY1
// Select SPI functionality for P0.0 to
//Write to GP0KEY2
Rev. PrA | Page 89 of 100
In slave mode, the SPICON register must be configured with
the phase and polarity of the expected input clock. The slave
accepts data from an external master up to 5.12 Mb.
In both master and slave modes, data are transmitted on one
edge of the SCL signal and sampled on the other. Therefore, it is
important that the polarity and phase are configured the same
for the master and slave devices.
SLAVE SELECT ( SS INPUT) PIN
In SPI slave mode, a transfer is initiated by the assertion of SS ,
which is an active low input signal. The SPI port then transmits
and receives 8-bit data until the transfer is concluded by
deassertion of SS . In slave mode, SS is always an input.
In SPI master mode, the SS is an active low output signal.It
asserts itself automatically at the beginning of a transfer and
deasserts itself upon completion.
CONFIGURING EXTERNAL PINS FOR SPI
FUNCTIONALITY
The SPI pins of the ADuC7060 device are P0[0:3].
P0.0 is the slave chip select pin. In slave mode, this pin is an
input and must be driven low by the master. In master mode,
this pin is an output and will go low at the beginning of a
transfer and high at the end of a transfer.
P0.1 is the SCL pin.
P0.2 is the master In, slave out (MISO) pin.
P0.3 is the master Out, slave in (MOSI) pin.
To configure P0[0:3] for SPI mode, Bit 0 to Bit 3 of the
GP0CON0 register must be set to 1. Bit 1 of the GP0CON1
Note that to write to GP0CON1, the GP0KEY1 register must be
set to 0x7 immediatley before writing to GP0CON1. Also, the
GP0KEY2 register must be set to 0x13 immediatley after
writing to GP0CON1. The following code example shows this
in detail:
2
C alternative function for P0[0...3]
ADuC7060/ADuC7061/ADuC7062
P0.3