aduc7062 Analog Devices, Inc., aduc7062 Datasheet - Page 79

• Manufacturer Part Number: aduc7062
• Description: Low-power, Precision Analog Microcontroller, Dual ?-? Adcs, Flash/ee, Arm7tdmi
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
I
The ADuC7060 incorporates an I
configured as a fully I
a fully I
data transfer, SDA and SCL, are configured in a wired-AND
format that allows arbitration in a multimaster system. These
pins require external pull-up resistors. Typical pull-up values
are between 4.7 kΩ and10 kΩ.
The I
programmed by the user. This ID can be modified any time a
transfer is not in progress. The user can configure the interface
to respond to four slave addresses.
The transfer sequence of an I
device initiating a transfer by generating a start condition while
the bus is idle. The master transmits the slave device address
and the direction of the data transfer (read or /write) during the
initial address transfer. If the master does not lose arbitration
and the slave acknowledges, the data transfer is initiated. This
continues until the master issues a stop condition and the bus
becomes idle.
The I
at any given time. The same I
support master and slave modes.
The I
features:
•
GP0CON0 = BIT1 + BIT3;
GP0KEY1 = 0x7;
GP0CON1
GP0KEY2 = 0x13;
2
C
Support for repeated start conditions. In master mode, the
ADuC7060 can be programmed to generate a repeated
start. In slave mode, the ADuC7060 recognizes repeated
start conditions.
2
2
2
C bus peripheral is address in the I
C peripheral can only be configured as a master or slave
C interface on the ADuC7060 includes the following
2
C bus-compatible slave device. The two pins used for
= BIT1;
2
C-compatible I
2
2
C system consists of a master
C channel cannot simultaneously
2
C peripheral that may
2
C bus master device or, as
// Select SPI/I
// Write to GP0KEY1
// Select I
// Write to GP0KEY2
2
C bus system is
2
C functionality for P0.1 and P0.3
Rev. PrA | Page 79 of 100
2
C alternative function for P0.1 and P0.3
•
•
•
•
•
•
•
Configuring External pins for I2C functionality
The I
the I
P0.1 and P0.3 for I2C mode, Bit 1 and Bit 3 of the GP0CON0
register must be set to 1. Bit 1 of the GP0CON1 register must
also be set to 1 to enable I
Note that to write to GP0CON1, the GP0KEY1 register must be
set to 0x7 immediatley before writing to GP0CON1. Also, the
GP0KEY2 register must be set to 0x13 immediatley after
writing to GP0CON1. The following code example shows this
in detail:
2
In master and slave mode, the part recognizes both 7-bit
and 10-bit bus addresses.
In I
reads from a single slave up to 512 bytes in a single transfer
sequence.
Clock stretching is supported in both master and slave
modes.
In slave mode, the ADuC7060 can be programmed to
return a no acknowledge (NACK). This allows the
validiation of checksum bytes at the end of I
Bus arbitration in master mode is supported.
Internal and external loopback modes are supported for
I
The transmit and receive circuits in both master and slave
mode contain 2-byte FIFOs. Status bits are available to the
user to control these FIFOs.
C clock signal and P0.3 is the I
2
2
C pins of the ADuC7060 device are P0.1 and P0.3. P0.1 is
C hardware testing. In loopback mode.
2
C master mode, the ADuC7060 supports continuous
ADuC7060/ADuC7061/ADuC7062
2
C mode.
2
C data signal. To configure
2
C transfers.