aduc7062 Analog Devices, Inc., aduc7062 Datasheet - Page 51

• Manufacturer Part Number: aduc7062
• Description: Low-power, Precision Analog Microcontroller, Dual ?-? Adcs, Flash/ee, Arm7tdmi
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
Using the DAC
The on-chip DAC architecture consists of a resistor string DAC
followed by an output buffer amplifier. The functional equivalent
is shown in the figure below:
The reference source for the DAC is user-selectable in software. It
can be either AV
•
•
•
The DAC may be configured in three different user modes:
normal mode, DAC interpolation mode, and op-amp mode.
Normal DAC Mode
In this mode of operation, the DAC is configured as a 12-bit
voltage output DAC. By default, the DAC buffer is enabled but,
the output buffer can be disabled. If the DAC output buffer is
disabled, the DAC is only capable of driving a capacitive load of
20 pF. The DAC buffer is disabled by setting the
DACBUFBYPASS bit in DACCON.
The DAC output buffer amplifier features a true, rail-to-rail
output stage implementation. This means that when unloaded,
each output is capable of swinging to within less than 5 mV of
both AV
(when driving a 5 kΩ resistive load to ground) is guaranteed
through the full transfer function except codes 0 to 100, and, in
0-to-AV
degradation near ground and V
output amplifier, and a general representation of its effects
(neglecting offset and gain error) is illustrated in Figure 15. The
dotted line in Figure 15 indicates the ideal transfer function, and
the solid line represents what the transfer function may look
like with endpoint nonlinearities due to saturation of the output
amplifier. Note that Figure 15 represents a transfer function in
In 0-to-AV
spans from 0 V to the voltage at the AVDD pin.
In VREF± and Ext_Ref2±.modes, the DAC output transfer
function spans from negative input voltage to the voltage
positive input pin. Note that these voltages must never go
below 0 V or above AV
In 0-to-V
from 0 V to the internal 1.2 V reference, V
DD
DD
and ground. Moreover, the DAC’s linearity specification
mode only, Code 3995 to Code 4095. Linearity
REF
DD
DD
mode, the DAC output transfer function spans
, VREF± or Ext_Ref2±.
mode, the DAC output transfer function
DD
.
DD
is caused by saturation of the
REF
.
Rev. PrA | Page 51 of 100
0-to-AV
modes (with V
lower nonlinearity is similar. However, the upper portion of the
transfer function follows the ideal line right to the end (V
case, not AV
The endpoint nonlinearities conceptually illustrated in Figure 15
worsen as a function of output loading. Most of the ADuC7060
data sheet specifications in normal mode assume a 5 kΩ
resistive load to ground at the DAC output. As the output is
forced to source or sink more current, the nonlinear regions at
the top or bottom (respectively) of Figure 15 become larger.
With larger current demands, this can significantly limit output
voltage swing.
DAC Interpolation Mode
In Interpolation mode, a higher DAC output resolution of 16-
bits is achieved with a longer update rate than normal mode.
The update rate is controlled by the Interpolation clock rate
selected in the DACCON register. In this mode, an external RC
filter is required to create a contstant voltage.
OP-AMP Mode
In op-amp mode, the DAC output buffer is used as an op-amp
with the DAC itself disabled.
ADC6 is the positive input to the op-amp, ADC7 is the negative
input and ADC8 is the output. In this mode, the DAC should be
powered down by setting Bit 9 of DACCON.
Figure 15. Endpoint Nonlinearities Due to Amplifier Saturation
AV
DD
DD
mode only. In 0-to-V
DD
ADuC7060/ADuC7061/ADuC7062
– 100mV
), showing no signs of endpoint linearity errors.
100mV
REF
AV
DD
< AV
0x00000000
DD
or Ext_Ref+/Ext_Ref2+ < AV
REF
or, VRef± and Ext_Ref2±
0x0FFF0000
REF
DD
), the
in this