aduc7062 Analog Devices, Inc., aduc7062 Datasheet - Page 32

• Manufacturer Part Number: aduc7062
• Description: Low-power, Precision Analog Microcontroller, Dual ?-? Adcs, Flash/ee, Arm7tdmi
• Manufacturer: Analog Devices, Inc.

ADuC7060/ADuC7061/ADuC7062
Table 31. Example Scenarios for Using Diagnostic Current Sources
Diagnostic Test
ADC0DIAG[1:0] = 0. Convert
ADC0/ADC1 as normal with
diagnostic currents disabled.
Enable 50 μA diagnostic current
source on ADC0 by setting
ADC0DIAG[1:0] = 1. Convert
ADC0 and ADC1.
Enable 50 μA diagnostic current
source on ADC0 by setting
ADC0DIAG[1:0] = 1. Convert
ADC0 and ADC1.
Convert ADC0 in single-ended
mode with diagnostic currents
disabled.
Enable 50 μA diagnostic current
source on both ADC0 and ADC1
by setting ADC0DIAG[1:0] = 3.
Convert ADC0 and ADC1.
Sinc3 Filter
The number entered into Bits[6:0] of the ADCFLT register sets
the decimation factor of the Sinc3 filter. See Table 32 and Table 33
for further details on the decimation factor values.
The range of operation of the Sinc3 filter (SF) word depends on
whether the chop function is enabled. With chopping disabled,
the minimum SF word allowed is 3 and the maximum is 127,
giving an ADC throughput range of 50 Hz to 2 kHz.
For details on how to calculate the ADC sampling frequency
based on the value programmed to the SF[6:0] in the ADCFLT
register, refer to Table 32 for more details.
ADC CHOPPING
The ADCs on the ADuC706x implement a chopping scheme
whereby the ADC repeatedly reverses its inputs. Therefore, the
decimated digital output values from the Sinc3 filter have a
positive and negative offset term associated with them. This
results in the ADC including a final summing stage that sums
and averages each value from the filter with previous filter
output values. This new value is then sent to the ADC data
MMR. This chopping scheme results in excellent dc offset and
offset drift specifications and is extremely beneficial in
applications where drift and noise rejection are required.
Programmable Gain Amplifier
The primary ADC incorporates an on-chip programmable gain
amplifier (PGA). The PGA can be programmed through 10
different settings giving a range of 1 to 512. The gain is
controlled by the ADC0PGA[3:0] bits in the ADC0CON MMR.
Excitation Sources
The ADuC706x contains two matched software configurable
current sources. These excitation currents are sourced from
Normal Result
Expected differential result
across ADC0/ADC1.
Main ADC changes by
ΔV = +50 μA × R1. For example,
~100 mV for R1 = 2 kΩ.
Main ADC changes by
ΔV = +50 μA × R1. For example,
~100 mV for R1 = 2 kΩ.
Expected voltage on ADC0.
Primary ADC changes by
ΔV = 50 μA × (R1-R2). That is,
~10 mV for 10% tolerance.
Rev. PrA | Page 32 of 100
Fault Result
Short circuit
Short circuit between ADC0 and
ADC1
Short circuit between R1_a and
R1_b
ADC0 open circuit or R1 open
circuit
R1 does not match R2
AVDD. They are individually configurable to give a current
range of 200 μA to 1 mA. The current step sizes are 200 μA.
These current sources can be used to excite an external resistive
bridge or RTD sensors. The IEXCON MMR controls the
excitation current sources. Bit 6 of IEXCON must be set to
enable Excitation Current Source 0. Similarly, Bit 7 must be set
to enable Excitation Current Source 1. The output current of
each current source is controlled by the IOUT[3:0] bits of this
register.
It is also possible to configure the excitation current sources to
output current to a single output pin, either IEXC0 or IEXC1,
by using the IEXC0_DIR and IEXC1_DIR bits of IEXCON. This
allows up to 2 mA to output current on a single excitation pin.
ADC Low Power Mode
The ADuC706x allows the primary and auxiliary ADCs to be
placed in Low-Power operating mode. When configured for
this mode, the ADC throughput time is reduced but, the power
consumption of the primary ADC is reduced by a factor of
about 4; the auxiliary ADC power consumption is reduced by a
factor of roughly 3. The maximum ADC conversion rate in
Low-Power mode is 2 kHz. The operating mode of the ADC’s is
controlled by the ADCMDE register. This register configures
the part for either normal mode (default), low power mode or
low-power-plus mode. Low-power plus mode is the same as
low-power mode except, the PGA is disabled.
To place the ADCs in low power mode, the following steps must
be completed:
•
•
ADCMDE[4:3]—Setting these bits enables normal mode,
low power mode, or low power-plus mode.
ADCMDE[5]—Clearing this bit is optional but it further
reduces power consumption by placing the internal refer-
Preliminary Technical Data
Detected
Measurement for Fault
Primary ADC reading ≈0 V
regardless of PGA setting.
Primary ADC reading ≈ 0 V
regardless of PGA setting.
Primary ADC reading ≈ 0 V
regardless of PGA setting.
Primary ADC reading = +full
scale, even on the lowest PGA
setting.
Primary ADC reading > 10 mV