aduc7062 Analog Devices, Inc., aduc7062 Datasheet - Page 56

• Manufacturer Part Number: aduc7062
• Description: Low-power, Precision Analog Microcontroller, Dual ?-? Adcs, Flash/ee, Arm7tdmi
• Manufacturer: Analog Devices, Inc.

ADuC7060/ADuC7061/ADuC7062
Priority Registers
The IRQ interrupt vector register, IRQVEC points to a memory
address containing a pointer to the interrupt service routine of
the currently active IRQ. This register should only be read when
an IRQ occurs and IRQ interrupt nesting has been enabled by
setting Bit 0 of the IRQCONN register.
IRQP0 Register
Name:
Address:
Default value:
Access:
Table 64. IRQP0 MMR Bit Designations
Bit
31:27
26:24
23
22:20
19
18:16
15
14:12
11:7
6:4
3:0
IRQP1 Register
Name:
Address:
Default value:
Access:
Name
Reserved
T3PI
Reserved
T2PI
Reserved
T1PI
Reserved
T0PI
Reserved
SWINTP
Reserved
IRQP0
0xFFFF0020
0x00000000
Read and write
IRQP1
0xFFFF0024
0x00000000
Read and write
Description
Reserved bits.
A priority level of 0 to 7 can be set
for Timer 3.
Reserved bit.
A priority level of 0 to 7 can be set
for Timer 2.
Reserved bit.
A priority level of 0 to 7 can be set
for Timer 1.
Reserved bit.
A priority level of 0 to 7 can be set
for Timer 0.
Reserved bits.
A priority level of 0 to 7 can be set
for the software interrupt source.
Interrupt 0 cannot be prioritized.
Rev. PrA | Page 56 of 100
Table 65. IRQP1 MMR Bit Designations
Bit
31
30
:28
27
26:24
23
22:20
19
18:16
15
14:12
11
10:8
7:0
IRQP2 Register
Name:
Address:
Default value:
Access:
Table 66. IRQP2 MMR Bit Designations
Bit
31:15
14:12
11
10:8
7
6:4
3
2:0
Name
Reserved
I2CMPI
Reserved
IRQ1PI
Reserved
IRQ0PI
Reserved
SPIMPI
Reserved
UARTPI
Reserved
ADCPI
Reserved
Name
Reserved
IRQ3PI
Reserved
IRQ2PI
Reserved
SPISPI
Reserved
I2CSPI
IRQP2
0xFFFF0028
0x00000000
Read and write
Preliminary Technical Data
Description
Reserved bit.
A priority level of 0 to 7 can be set
for I
Reserved bit.
A priority level of 0 to 7 can be set
for IRQ1.
Reserved bit.
A priority level of 0 to 7 can be set
for IRQ0.
Reserved bit.
A priority level of 0 to 7 can be set
for SPI master.
Reserved bit.
A priority level of 0 to 7 can be set
for UART.
Reserved bit.
A priority level of 0 to 7 can be set
for the ADC interrupt source.
Reserved bits.
Description
Reserved bit.
A priority level of 0 to 7 can be set
for IRQ3.
Reserved bit.
A priority level of 0 to 7 can be set
for IRQ2.
Reserved bit.
A priority level of 0 to 7 can be set
for SPI slave.
Reserved bit.
A priority level of 0 to 7 can be set
for I
2
2
C master.
C slave.