aduc7062 Analog Devices, Inc., aduc7062 Datasheet - Page 26

• Manufacturer Part Number: aduc7062
• Description: Low-power, Precision Analog Microcontroller, Dual ?-? Adcs, Flash/ee, Arm7tdmi
• Manufacturer: Analog Devices, Inc.

ADuC7060/ADuC7061/ADuC7062
RESET
There are four kinds of reset: external reset, power-on-reset,
watchdog reset, and software reset. The RSTSTA register
indicates the source of the last reset and can be written by user
code to initiate a software reset event.
The bits in this register can be cleared to 0 by writing to the
RSTCLR MMR at 0xFFFF0234. The bit designations in
RSTCLR mirror those of RSTSTA. These registers can be used
during a reset exception service routine to identify the source of
the reset. The implications of all four kinds of reset events are
tabulated in Table 24.
RSTSTA Register
Name:
Address:
Default value:
Access:
Function:
Table 24. Device Reset Implications
RESET
POR
Watchdog
Software
External
Pin
Reset External
Pins to Default
State
Yes
Yes
Yes
Yes
RSTSTA
0xFFFF0230
Depends on type of reset
Read/write access
This 8-bit register indicates the source of the
last reset event and can be written by user code
to initiate a software reset.
Kernel
Executed
Yes
Yes
Yes
Yes
Reset All
External MMRs
(Excluding
RSTSTA)
Yes
Yes
Yes
Yes
Rev. PrA | Page 26 of 100
Peripherals
Reset
Yes
Yes
Yes
Yes
RSTCLR Register
Name:
Address:
Access:
Function:
Table 23. RSTSTA/RSTCLR MMR Bit Designations
Bit
7 to 4
3
2
1
0
1
clear this bit generates a software reset.
If the software reset bit in RSTSTA is set, any write to RSTCLR that does not
RSTCLR
0xFFFF0234
Write only
This 8-bit write only register clears the
corresponding bit in RSTSTA.
Description
Not Used. These bits are not used and always
read as 0.
External Reset.
Automatically set to 1 when an external reset
occurs.
This bit is cleared by setting the corresponding bit
in RSTCLR.
Software Reset.
This bit is set to 1 by user code to generate a soft-
ware reset.
This bit is cleared by setting the corresponding bit
in RSTCLR.
Watchdog Timeout.
Automatically set to 1 when a watchdog timeout
occurs.
Cleared by setting the corresponding bit in RSTCLR.
Power-On Reset.
Automatically Set when a power-on-reset occurs.
Cleared by setting the corresponding bit in RSTCLR.
Watchdog
Timer Reset
Yes
No
No
No
Preliminary Technical Data
1
RAM
Valid
Yes/No
Yes
Yes
Yes
RSTSTA (Status
After Reset
Event)
RSTSTA[0] = 1
RSTSTA[1] = 1
RSTSTA[2] = 1
RSTSTA[3] = 1