z8fmc16100 ZiLOG Semiconductor, z8fmc16100 Datasheet - Page 138

• Manufacturer Part Number: z8fmc16100
• Description: Z8 Encore Motor Control Flash Mcus
• Manufacturer: ZiLOG Semiconductor

PS024611-0408
System
Clock
Architecture
Operation
LIN-UART
•
•
Figure 17
network.
Figure 18
filter in this example is a 2-bit up/down counter which saturates at
counter is shown for convenience, the operation of wider counters is similar. The output of
the filter switches from 1 to 0 when the counter counts down from
switches from 0 to 1 when the counter counts up from
the receive data by three System Clock cycles.
The
time. The presence of noise (
sampled data is incorrect, just that the filter is not in its "saturated" state of all 1’s or all 0’s.
If
ModeStatus[4:0]
the network can be obtained.
FiltSatB = 1
The digital filter output features hysteresis.
Provides an active low Saturated State output (
presence of noise.
FiltSatB
displays how the noise filter is integrated with the LIN-UART for use on a LIN
displays the operation of the noise filter both with and without noise. The noise
Figure 17. Noise Filter System Block Diagram
NFEN, NFCTL
FiltSatB
signal is checked when the filtered RxD is sampled in the center of the bit
RxD
TxD
, when RxD is sampled during a receive character, the
field is set. By observing this bit, an indication of the level of noise in
FiltSatB = 1
Noise
Filter
at center of bit time) does not mean the
FiltSatB
GPIO
10b
RxD
TxD
to
) used as an indication of the
11b.
Product Specification
The noise filter delays
00b
RxD
TxD
Transceiver
01b
and
LIN
NE
11b
to
Architecture
00b
bit in the
. A 2-bit
and
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