z8fmc16100 ZiLOG Semiconductor, z8fmc16100 Datasheet - Page 264

• Manufacturer Part Number: z8fmc16100
• Description: Z8 Encore Motor Control Flash Mcus
• Manufacturer: ZiLOG Semiconductor

Table 136. OCD Status Register (OCDSTAT)
PS024611-0408
BITS
FIELD
RESET
R/W
OCD Status Register
IDLE
0 = OCDCNTR is setup as counter
1 = OCDCNTR generates hardware break when PC == OCDCNTR
BRKZRO—Break when OCDCNTR ==
If this bit is set, then the OCD automatically sets the DBGMODE bit when the OCD-
CNTR register counts down to
when the part leaves DEBUG Mode.
0 = OCD does not generate BRK when OCDCNTR decrements to
1 = OCD sets DBGMODE to 1 when OCDCNTR decrements to
Reserved—Must be 0.
RST—Reset
Setting this bit to 1 resets the device. The controller goes through a normal POR sequence
with the exception that the OCD is not reset. This bit is automatically cleared to 0 when the
reset finishes.
0 = No effect.
1 = Reset the device.
The OCD Status register
the debugger and the system.
IDLE—CPU idle
This bit is set if the part is in DEBUG mode (DBGMODE is 1) or if a BRK instruction has
occurred since the last time OCDCTL was written. This can be used to determine if the
CPU is running or if it is idle.
0 = The eZ8 CPU is running.
1 = The eZ8 CPU is either stopped or looping on a BRK instruction.
HALT—HALT Mode
0 = The device is not in HALT mode.
1 = The device is in HALT mode.
RPEN—Read Protect Option Bit Enabled
0 = The Read Protect Option Bit is disabled (Flash option bit is 1).
R
7
0
HALT
R
6
0
RPEN
R
5
0
(Table
0000H
136) reports status information about the current state of
4
. If this bit is set, the OCDCNTR register is not reset
0000H
3
Z8FMC16100 Series Flash MCU
Reserved
R
2
0
Product Specification
0000H
0000H
OCD Status Register
1
0
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