z8fmc16100 ZiLOG Semiconductor, z8fmc16100 Datasheet - Page 195

• Manufacturer Part Number: z8fmc16100
• Description: Z8 Encore Motor Control Flash Mcus
• Manufacturer: ZiLOG Semiconductor

Table 93. I
BITS
FIELD
RESET
R/W
ADDR
PS024611-0408
2
C Interrupt Status Register (I2CISTAT)
TDRE
R
7
1
TDRE—Transmit Data Register Empty
When the I
When set, this bit causes the I
Controller is shifting in data during the reception of a byte or when shifting an address and
the RD bit is set. This bit clears by writing to the I2CDATA register.
RDRF—Receive Data Register Full
This bit is set = 1 when the I
byte of data. When asserted, this bit causes the I
This bit clears by reading the I2CDATA register.
SAM—Slave Address Match
This bit is set = 1 if the I
which matches the unique Slave address or General Call Address (if enabled by the
bit in the I
achieved on both address bytes. When this bit is set, the
This bit clears by reading the I2CISTAT register.
GCA—General Call Address
This bit is set in Slave mode when the General Call Address or START byte is recognized
(in either 7 or 10 bit Slave mode). The
enable recognition of the General Call Address and START byte. This bit clears when
IEN
General Call Address is distinguished from a START byte by the value of the RD bit (RD
= 0 for General Call Address, 1 for START byte).
RD—Read
This bit indicates the direction of transfer of the data. It is set when the Master is reading
data from the Slave. This bit matches the least-significant bit of the address byte after the
START condition occurs (for both Master and Slave modes). This bit clears when IEN = 0
and is updated following the first address byte of each transaction.
ARBLST—Arbitration Lost
This bit is set when the I
(outputs a 1 on SDA and receives a 0 on SDA). The ARBLST bit clears when the
I2CISTAT register is read.
= 0 and is updated following the first address byte of each Slave mode transaction. A
RDRF
2
R
6
0
C Mode register). In 10-bit addressing mode, this bit is not set until a match is
2
C Controller is enabled, this bit is 1 when the I
SAM
R
5
0
2
C Controller is enabled in Slave mode and an address is received
2
C Controller is enabled in Master mode and loses arbitration
2
C Controller is enabled and the I
2
C Controller to generate an interrupt, except when the I
GCA
R
4
0
F51H
GCE
bit in the I
RD
R
3
0
2
C Controller to generate an interrupt.
Z8FMC16100 Series Flash MCU
ARBLST
2
C Mode register must be set to
RD
R
2
0
2
and
2
C Controller has received a
C Data register is empty.
Product Specification
I
2
C Interrupt Status Register
GCA
SPRS
bits are also valid.
R
1
0
NCKI
R
0
0
GCE
2
C
183