z8fmc16100 ZiLOG Semiconductor, z8fmc16100 Datasheet - Page 146

• Manufacturer Part Number: z8fmc16100
• Description: Z8 Encore Motor Control Flash Mcus
• Manufacturer: ZiLOG Semiconductor

Table 72. MultiProcessor Control Register (U0CTL1 with MSEL = 000b)
PS024611-0408
BITS
FIELD
RESET
R/W
ADDR
LIN-UART Control 1 Registers
MPMD[1]
R/W
7
0
must be timed by software before writing a new byte to be transmitted to the transmit data
register. In LIN mode, the master sends a Break character by asserting
of the break is timed by hardware, and the
Break is completed. The duration of the Break is determined by the
of the LIN Control register. One or two stop bits are automatically provided by the hard-
ware in LIN mode as defined by the
0 = No break is sent.
1 = The output of the transmitter is 0.
STOP—Stop Bit Select
0 = The transmitter sends one stop bit.
1 = The transmitter sends two stop bits.
LBEN—Loop Back Enable
0 = Normal operation.
1 = All transmitted data is looped back to the receiver within the IrDA module.
Multiple registers
register selected is determined by the Mode Select (MSEL) field. These registers provide
additional control over LIN-UART operation.
Multiprocessor Control Register
When MSEL =
UART MULTIPROCESSOR mode, IRDA mode, baud rate timer mode as well as other fea-
tures which applies to multiple modes.
MPMD[1:0]—MULTIPROCESSOR Mode
If MULTIPROCESSOR (9-bit) mode is enabled,
00 = The LIN-UART generates an interrupt request on all received bytes (data and
01 = The LIN-UART generates an interrupt request only on received address bytes.
10 = The LIN-UART generates an interrupt request when a received address byte matches
address).
MPEN
R/W
6
0
000b
(Table 72
MPMD[0]
, the Multiprocessor Control register
R/W
5
0
through
F43H with MSEL = 000b
MPBT
R/W
4
0
STOP
Table
bit.
74) are accessible by a single bus address. The
DEPOL
SBRK
R/W
3
0
bit is deasserted by hardware when the
Z8FMC16100 Series Flash MCU
BRGCTL
R/W
2
0
(Table
LIN-UART Control 1 Registers
Product Specification
72) provides control for
TxBreakLength
RDAIRQ
R/W
SBRK
1
0
. The duration
IREN
R/W
0
0
field
134