z8fmc16100 ZiLOG Semiconductor, z8fmc16100 Datasheet - Page 186

• Manufacturer Part Number: z8fmc16100
• Description: Z8 Encore Motor Control Flash Mcus
• Manufacturer: ZiLOG Semiconductor

PS024611-0408
2. The software writes
3. The software asserts the
4. The I
5. The I
6. After the first bit has been shifted out, a transmit interrupt is asserted.
7. The software responds by writing the least significant eight bits of address to the I
8. The I
9. The I
10. The I
11. The I
12. The software responds by setting the
13. The software writes
14. To read only one byte, the software responds by setting the
15. After the I
as a slave (but not for the remote slave). The software asserts the IEN bit in the I
Control register.
0 (write) to the I
register.
Data register.
High period of SCL.
If the slave does not acknowledge the address byte, the I
bit in the I
register. The software responds to the Not Acknowledge interrupt by setting the
bit and clearing the
sends the
transaction is complete, and the following steps can be ignored.
register (the lower byte of the 10-bit address).
the I
a repeated
I
register.
transfer), the I
the next High period of SCL.
If the slave does not acknowledge the address byte, the I
bit in the I
register. The software responds to the Not Acknowledge interrupt by setting the
bit and clearing the
2
C Data register.
2
2
2
2
2
2
2
C controller generates a transmit interrupt.
C controller sends a
C controller loads the I
C controller completes shifting of the first address byte.
C slave sends an Acknowledge by pulling the SDA signal Low during the next
C controller loads the I
C controller shifts out the next eight bits of the address. After the first bit shifts,
STOP
2
2
2
START
C Status register, sets the
C Status register, sets the
C controller shifts out the address bits listed in Step 9 (the second address
2
C slave sends an Acknowledge by pulling the SDA signal Low during
condition on the bus and clears the
2
C Data register.
condition.
TXI
TXI
11110b
11110b
bit. The I
bit. The I
START
START
, followed by the 2-bit slave address and a 1 (Read) to the
, followed by the two most-significant address bits and a
2
2
C Shift register with the contents of the I
C Shift register with the contents of the I
bit of the I
2
2
condition.
C controller flushes the Transmit Data register,
C controller flushes the Transmit Data register,
ACKV
ACKV
START
2
bit and clears the
bit, and clears the
C Control register.
bit of the I
STOP
2
C Control register to generate
2
2
and
C controller sets the NCKI
C controller sets the NCKI
NAK
Product Specification
ACK
ACK
NCKI
bit of the I
bit in the I
bit in the I
Master Transactions
bits. The
2
2
C Data
C Data
2
C Control
2
2
C State
C State
STOP
STOP
2
C
2
C
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