z8fmc16100 ZiLOG Semiconductor, z8fmc16100 Datasheet - Page 199
z8fmc16100
Manufacturer Part Number
z8fmc16100
Description
Z8 Encore Motor Control Flash Mcus
Manufacturer
ZiLOG Semiconductor
Datasheet
1.Z8FMC16100.pdf
(381 pages)
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Table 97. I
BITS
FIELD
RESET
R/W
ADDR
PS024611-0408
2
C State Register (I2CSTATE) - Description when DIAG = 0
ACKV
R
7
0
When the
on the internal state of the I
each bit follows this table.
When the
controller state machine
ACKV—ACK Valid
This bit is set if sending data (Master or Slave) and the
the byte just transmitted. This bit can be monitored if it is appropriate for software to
verify the
data register must not be written when
assert. This bit clears when transmission of the next byte begins or the transaction is ended
by a STOP or RESTART condition.
ACK—Acknowledge
This bit indicates the status of the Acknowledge for the last byte transmitted or received.
This bit is set for an Acknowledge and cleared for a Not Acknowledge condition.
AS—Address State
This bit is active High while the address is being transferred on the I
DS—Data State
This bit is active High while the data is being transferred on the I
10B—This bit indicates whether a 10 or 7-bit address is being transmitted when operating
as a Master. After the
11110B
RSTR—RESTART
This bit is updated each time a STOP or RESTART interrupt occurs (
I2CISTAT register).
0 = Stop condition
1 = Restart condition
SCLOUT—Serial Clock Output
Current value of Serial Clock being output onto the bus. The actual values of the SCL and
SDA signals on the I2C bus can be observed via the GPIO Input register.
, this bit is set. When set, it is reset once the address has been sent.
ACK
DIAG
DIAG
ACK
R
6
0
value before writing the next byte to be sent. To operate in this mode, the
bit of the I
bit of the I
AS
START
R
5
0
(Table
2
2
C Mode register is set, this register returns the value of the I
2
C Mode register is cleared, this register provides information
C controller and I
bit is set, if the five most-significant bits of the address are
98).
DS
R
4
0
F55H
TDRE
10B
asserts; instead, software waits for
2
R
C bus
3
0
Z8FMC16100 Series Flash MCU
(Table
ACK
RSTR
R
2
0
bit in this register is valid for
97). A detailed discussion of
Product Specification
2
C bus.
SCLOUT
2
C bus.
R
X
1
I
SPRS
2
C State Register
bit set in
BUSY
ACKV
X
R
0
2
to
C
187
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