mc56f8335 Freescale Semiconductor, Inc, mc56f8335 Datasheet - Page 107

• Manufacturer Part Number: mc56f8335
• Description: 16-bit Digital Signal Controller
• Manufacturer: Freescale Semiconductor, Inc

6.5.6.7
This bit controls the pull-up resistors on the EXTBOOT pin.
Note:
6.5.6.8
This bit controls the pull-up resistors on the FAULTB0, FAULTB1, FAULTB2, and FAULTB3 pins.
6.5.6.9
This bit controls the pull-up resistors on the FAULTA0, FAULTA1, and FAULTA2 pins.
6.5.6.10
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.6.11
This bit controls the pull-up resistors on the WR and RD pins.
6.5.6.12
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.6.13
This bit controls the pull-up resistors on the TRST, TMS and TDI pins.
6.5.6.14
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.7
The CLKO select register can be used to multiplex out any one of the clocks generated inside the clock
generation and SIM modules. The default value is SYS_CLK. This path has been optimized in order to
minimize any delay and clock duty cycle distortion. All other clocks primarily muxed out are for test
purposes only, and are subject to significant phase shift at high frequencies.
The upper four bits of the GPIOB register can function as GPIO, [A23:A20], or as additional clock output
signals. GPIO has priority and is enabled/disabled via the GPIOB_PER. If GPIOB[7:4] are programmed
to operate as peripheral outputs, then the choice between [A23:A20] and additional clock outputs is done
here in the CLKOSR. The default state is for the peripheral function of GPIOB[7:4] to be programmed as
[A23:A20]. This can be changed by altering [A23:A20], as shown in
Freescale Semiconductor
Preliminary
Base + $A
RESET
Read
Write
In this package, this input pin is double-bonded with the adjacent V
changed to a 1 in order to reduce power consumption.
CLKO Select Register (SIM_CLKOSR)
XBOOT—Bit 9
PWMB—Bit 8
PWMA0—Bit 7
Reserved—Bit 6
CTRL—Bit 5
Reserved—Bit 4
JTAG—Bit 3
Reserved—Bit 2–0
15
0
0
14
0
0
Figure 6-9 CLKO Select Register (SIM_CLKOSR)
13
0
0
12
0
0
56F8335 Technical Data, Rev. 5
11
0
0
10
0
0
A23
9
0
A22
8
0
A21
7
0
A20
6
0
Figure
CLK
DIS
5
1
SS
pin and this bit should be
6-9.
4
0
3
0
CLKOSEL
2
0
Register Descriptions
1
0
0
0
107