mc56f8335 Freescale Semiconductor, Inc, mc56f8335 Datasheet - Page 115

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mc56f8335

Manufacturer Part Number
mc56f8335
Description
16-bit Digital Signal Controller
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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6.7 Power-Down Modes Overview
The 56F8335/56F8135 operate in one of three power-down modes, as shown in
All peripherals, except the COP/watchdog timer, run off the IPBus clock frequency, which is the same as
the main processor frequency in this architecture. The maximum frequency of operation is
SYS_CLK = 60MHz.
Freescale Semiconductor
Preliminary
Run
Wait
Stop
Mode
Active
Core and memory
clocks disabled
System clocks continue to be generated in
the SIM, but most are gated prior to
reaching memory, core and peripherals.
Core Clocks
Table 6-3 Clock Operation in Power-Down Modes
Active
Active
Peripheral Clocks
56F8335 Technical Data, Rev. 5
Device is fully functional
Peripherals are active and can produce interrupts if
they have not been masked off.
Interrupts will cause the core to come out of its
suspended state and resume normal operation.
Typically used for power-conscious applications.
The only possible recoveries from Stop mode are:
1. CAN traffic (1st message will be lost)
2. Non-clocked interrupts
3. COP reset
4. External reset
5. Power-on reset
Description
Table 6-3
Power-Down Modes Overview
.
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