mc56f8335 Freescale Semiconductor, Inc, mc56f8335 Datasheet - Page 110
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mc56f8335
Manufacturer Part Number
mc56f8335
Description
16-bit Digital Signal Controller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC56F8335.pdf
(160 pages)
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6.5.8.1
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.8.2
This bit selects the alternate function for GPIOC3.
6.5.8.3
This bit selects the alternate function for GPIOC2.
6.5.8.4
This bit selects the alternate function for GPIOC1.
110
1. This applies to the four pins that serve as Quad Decoder / Quad Timer / SPI / GPIOC functions. A separate set of control
2. Reset configuration
3. Quad Decoder pins are always inputs and function in conjunction with the Quad Timer pins.
•
•
•
•
Quad Timer Input /
Quad Decoder
Input
Quad Timer
Output / Quad
Decoder Input
SPI input
SPI output
Base + $B
bits is used for each pin.
Pin Function
RESET
Read
Write
0 = HOME1/TB3 (default - see “Switch Matrix Mode” bits of the Quad Decoder DECCR register in the
56F8300 Peripheral User’s Manual)
1 = SS1
0 = INDEX1/TB2 (default)
1 = MISO1
2
Reserved—Bits 15–4
GPIOC3 (C3)—Bit 3
GPIOC2 (C2)—Bit 2
GPIOC1 (C1)—Bit 1
3
15
0
0
Figure 6-11 GPIO Peripheral Select Register (SIM_GPS)
14
Table 6-2 Control of Pads Using SIM_GPS Control
0
0
1
1
1
1
13
0
0
12
—
—
—
—
0
0
Control Registers
11
0
0
56F8335 Technical Data, Rev. 5
10
0
0
0
0
1
1
9
0
0
8
0
0
—
—
0
1
7
0
0
6
0
0
See the “Switch Matrix for Inputs to the Timer”
table in the 56F8300 Peripheral User Manual
for the definition of timer inputs based on the
Quad Decoder mode configuration.
See SPI controls for determining the direction
of each of the SPI pins.
5
0
0
4
0
0
Comments
C3
3
0
1
Freescale Semiconductor
C2
2
0
C1
1
0
Preliminary
C0
0
0