mc56f8335 Freescale Semiconductor, Inc, mc56f8335 Datasheet - Page 31

• Manufacturer Part Number: mc56f8335
• Description: 16-bit Digital Signal Controller
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
Preliminary
(GPIOE10)
(GPIOE11)
(GPIOE12)
(GPIOE13)
RESET
Signal
Name
RSTO
IRQA
IRQB
TD0
TD1
TD2
TD3
Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued)
Pin No.
107
108
109
110
52
53
78
77
Schmitt
Schmitt
Schmitt
Schmitt
Output
Output
Output
Input/
Input/
Type
Input
Input
enabled
enabled
enabled
56F8335 Technical Data, Rev. 5
During
pull-up
pull-up
pull-up
Output
Reset
State
Input,
Input,
Input,
TD0 - TD3 — Timer D, Channels 0, 1, 2 and 3
Port E GPIO — These GPIO pins can be individually
programmed as input or output pins.
At reset, these pins default to Timer functionality.
To deactivate the internal pull-up resistor, clear the appropriate
bit of the GPIOE_PUR register. See
External Interrupt Request A and B — The IRQA and IRQB
inputs are asynchronous external interrupt requests during Stop
and Wait mode operation. During other operating modes, they
are synchronized external interrupt requests, which indicate an
external device is requesting service. They can be programmed
to be level-sensitive or negative-edge triggered.
To deactivate the internal pull-up resistor, set the IRQ bit in the
SIM_PUDR register. See
Reset — This input is a direct hardware reset on the processor.
When RESET is asserted low, the device is initialized and placed
in the reset state. A Schmitt trigger input is used for noise
immunity. The internal reset signal will be deasserted
synchronous with the internal clocks after a fixed number of
internal clocks.
To ensure complete hardware reset, RESET and TRST should
be asserted together. The only exception occurs in a debugging
environment when a hardware device reset is required and the
JTAG/EOnCE module must not be reset. In this case, assert
RESET, but do not assert TRST.
Note: The internal Power-On Reset will assert on initial
power-up.
To deactivate the internal pull-up resistor, set the RESET bit in
the SIM_PUDR register. See
Reset Output — This output reflects the internal reset state of
the chip.
Signal Description
Part 6.5.6
Part
6.5.6. for details.
for details.
Part 6.5.6
for details.
Signal Pins
31