mc56f8335 Freescale Semiconductor, Inc, mc56f8335 Datasheet - Page 98

• Manufacturer Part Number: mc56f8335
• Description: 16-bit Digital Signal Controller
• Manufacturer: Freescale Semiconductor, Inc

5.6.30
5.6.30.1
This read-only bit reflects the state of the interrupt to the 56800E core.
5.6.30.2
These read-only bits reflect the state of the new interrupt priority level bits being presented to the 56800E
core at the time the last IRQ was taken. This field is only updated when the 56800E core jumps to a new
interrupt service routine.
Note:
5.6.30.3
This read-only field shows the vector number (VAB[7:1]) used at the time the last IRQ was taken. This
field is only updated when the 56800E core jumps to a new interrupt service routine.
Note:
5.6.30.4
This bit allows all interrupts to be disabled.
5.6.30.5
This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing.
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Base + $1D
RESET
Read
Write
0 = No interrupt is being sent to the 56800E core
1 = An interrupt is being sent to the 56800E core
00 = Required nested exception priority levels are 0, 1, 2, or 3
01 = Required nested exception priority levels are 1, 2, or 3
10 = Required nested exception priority levels are 2 or 3
11 = Required nested exception priority level is 3
0 = Normal operation (default)
1 = All interrupts disabled
ITCN Control Register (ICTL)
Nested interrupts may cause this field to be updated before the original interrupt service routine can
read it.
Nested interrupts may cause this field to be updated before the original interrupt service routine can
read it.
Interrupt (INT)—Bit 15
Interrupt Priority Level (IPIC)—Bits 14–13
Vector Number - Vector Address Bus (VAB)—Bits 12–6
Interrupt Disable (INT_DIS)—Bit 5
Reserved—Bit 4
INT
15
0
14
0
IPIC
13
0
Figure 5-26 ITCN Control Register (ICTL)
12 11 10
1
0
56F8335 Technical Data, Rev. 5
0
VAB
9
0
8
0
7
0
6
0
INT_DIS
5
0
4
1
1
IRQB STATE
3
1
IRQA STATE
Freescale Semiconductor
2
1
IRQB
EDG
1
0
Preliminary
IRQA
EDG
0
0