mc56f8335 Freescale Semiconductor, Inc, mc56f8335 Datasheet - Page 144
mc56f8335
Manufacturer Part Number
mc56f8335
Description
16-bit Digital Signal Controller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC56F8335.pdf
(160 pages)
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10.13 Controller Area Network (CAN) Timing
Note: CAN is NOT available in the 56F8135 device.
10.14 JTAG Timing
144
1. TCK frequency of operation must be less than 1/8 the processor rate.
2. T = processor clock period (nominally 1/60MHz)
TCK frequency of operation
using EOnCE
TCK frequency of operation not
using EOnCE
TCK clock pulse width
TMS, TDI data set-up time
TMS, TDI data hold time
TCK low to TDO data valid
TCK low to TDO tri-state
TRST assertion time
CAN receive
1. Parameters listed are guaranteed by design
Baud Rate
Bus Wake Up detection
CAN_RX
data pin
(Input)
Characteristic
Characteristic
1
1
Figure 10-17 Bus Wake Up Detection
T
Symbol
BR
WAKEUP
CAN
Symbol
Table 10-21 CAN Timing
Table 10-22 JTAG Timing
t
TRST
t
f
f
t
t
t
56F8335 Technical Data, Rev. 5
t
PW
OP
OP
DH
DS
DV
TS
T
Min
—
5
WAKEUP
Min
2T
DC
DC
50
—
—
5
5
2
SYS_CLK/8
SYS_CLK/4
Max
Max
30
30
—
—
—
—
—
1
1
MHz
MHz
Unit
Mbps
ns
ns
ns
ns
ns
ns
Unit
μs
Freescale Semiconductor
See Figure
See Figure
10-17
10-18
10-18
10-18
10-19
10-19
10-19
10-19
10-20
—
Preliminary