mc56f8335 Freescale Semiconductor, Inc, mc56f8335 Datasheet - Page 4

• Manufacturer Part Number: mc56f8335
• Description: 16-bit Digital Signal Controller
• Manufacturer: Freescale Semiconductor, Inc

Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . . 5
Part 2: Signal/Connection Descriptions . . 14
Part 3: On-Chip Clock Synthesis (OCCS) . 33
Part 4: Memory Map. . . . . . . . . . . . . . . . . . . 35
Part 5: Interrupt Controller (ITCN) . . . . . . . . 71
Part 6: System Integration Module (SIM) . 100
Part 7: Security Features . . . . . . . . . . . . . 117
4
1.1. 56F8335/56F8135 Features . . . . . . . . . . . . . . .5
1.2. Device Description . . . . . . . . . . . . . . . . . . . . . 7
1.3. Award-Winning Development Environment . . .9
1.4. Architecture Block Diagram . . . . . . . . . . . . . . . 9
1.5. Product Documentation . . . . . . . . . . . . . . . . . 12
1.6. Data Sheet Conventions . . . . . . . . . . . . . . . . 13
2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2. Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.2. External Clock Operation . . . . . . . . . . . . . . . 33
3.3. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.2. Program Map. . . . . . . . . . . . . . . . . . . . . . . . . 36
4.3. Interrupt Vector Table . . . . . . . . . . . . . . . . . . .37
4.4. Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.5. Flash Memory Map . . . . . . . . . . . . . . . . . . . . 42
4.6. EOnCE Memory Map . . . . . . . . . . . . . . . . . . .43
4.7. Peripheral Memory Mapped Registers . . . . . .44
4.8. Factory Programmed Memory. . . . . . . . . . . . 71
5.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.3. Functional Description . . . . . . . . . . . . . . . . . . 71
5.4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 73
5.5. Operating Modes . . . . . . . . . . . . . . . . . . . . . . 73
5.6. Register Descriptions . . . . . . . . . . . . . . . . . . .74
5.7. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
6.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.3. Operating Modes . . . . . . . . . . . . . . . . . . . . . 101
6.4. Operating Mode Register . . . . . . . . . . . . . . 101
6.5. Register Descriptions . . . . . . . . . . . . . . . . . 102
6.6. Clock Generation Overview. . . . . . . . . . . . . 114
6.7. Power-Down Modes Overview . . . . . . . . . . 115
6.8. Stop and Wait Mode Disable Function . . . . 116
6.9. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
7.1. Operation with Security Enabled . . . . . . . . .117
7.2. Flash Access Blocking Mechanisms . . . . . .117
56F8335 Technical Data, Rev. 5
Table of Contents
Part 8: General Purpose Input/Output
Part 9: Joint Test Action Group (JTAG) . . 125
Part 10: Specifications. . . . . . . . . . . . . . . . 126
Part 11: Packaging . . . . . . . . . . . . . . . . . . 152
Part 12: Design Considerations . . . . . . . . 159
Part 13: Ordering Information . . . . . . . . . . 159
8.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 120
8.2. Memory Maps . . . . . . . . . . . . . . . . . . . . . . . 120
8.3. Configuration . . . . . . . . . . . . . . . . . . . . . . . . 120
9.1. JTAG Information . . . . . . . . . . . . . . . . . . . . 125
10.1. General Characteristics. . . . . . . . . . . . . . . 126
10.2. DC Electrical Characteristics. . . . . . . . . . . 130
10.3. AC Electrical Characteristics . . . . . . . . . . . 134
10.4. Flash Memory Characteristics . . . . . . . . . . 134
10.5. External Clock Operation Timing . . . . . . . 135
10.6. Phase Locked Loop Timing. . . . . . . . . . . . 135
10.7. Crystal Oscillator Timing . . . . . . . . . . . . . . 136
10.8. Reset, Stop, Wait, Mode Select
10.9. Serial Peripheral Interface (SPI) Timing . . . 138
10.10. Quad Timer Timing . . . . . . . . . . . . . . . . . 142
10.11. Quadrature Decoder Timing . . . . . . . . . . . 142
10.12. Serial Communication Interface
10.13. Controller Area Network (CAN) Timing . . 144
10.14. JTAG Timing . . . . . . . . . . . . . . . . . . . . . . 144
10.15. Analog-to-Digital Converter (
10.16. Equivalent Circuit for ADC Inputs . . . . . . 148
10.17. Power Consumption . . . . . . . . . . . . . . . . 149
11.1. 56F8335 Package and
11.2. 56F8135 Package and
12.1. Thermal Design Considerations . . . . . . . . . 159
12.2. Electrical Design Considerations . . . . . . . 159
12.3. Power Distribution and I/O Ring
(GPIO) . . . . . . . . . . . . . . . . . . . . . . 120
and Interrupt Timing . . . . . . . . . . . 136
(SCI) Timing . . . . . . . . . . . . . . . . . 143
ADC) Parameters . . . . . . . . . . . . . 146
Pin-Out Information . . . . . . . . . . . . 152
Pin-Out Information . . . . . . . . . . . . 155
Implementation . . . . . . . . . . . . . . . 159
Freescale Semiconductor
Preliminary