zl50416 Zarlink Semiconductor, zl50416 Datasheet - Page 102

• Manufacturer Part Number: zl50416
• Description: Managed 16-port 10/100 M + 2-port 1 G Ethernet Switch
• Manufacturer: Zarlink Semiconductor

D12
E12
C8
A9
B9
Fast Ethernet Access Ports [15:0] RMII
R28
P28
R29
AF21, AJ19, AF18,
AJ17, AJ15, AF15,
AJ13, AF12, AJ11,
AJ9, AF9, AJ7, AF6,
AJ5, AJ3, AF1
AE21, AH19, AH20,
AH17, AH15, AE15,
AH13, AE12, AH11,
AH9, AE9, AH7, AE6,
AH5, AH2, AF2
AH21, AF19, AF17,
AG17, AG15, AF14,
AG13, AF11, AG11,
AG9, AF8, AG7, AF5,
AG5, AH3, AF3
AE20, AJ18, AJ21,
AJ16, AJ14, AE14,
AJ12, AE11, AJ10,
AJ8, AE8, AJ6, AE5,
AJ4, AG1, AE1
AE18, AG18, AE16,
AG16, AG14, AE13,
AG12, AE10, AG10,
AG8, AE7, AG6, AE4,
AG4, AG3, AE3
Ball No(s)
LA_WE0#
LA_WE1#
LA_OE#
LA_OE0#
LA_OE1#
M_MDC
M_MDIO
M_CLKI
M[15:0]_RXD[1]
M[15:0]_RXD[0]
M[15:0]_CRS_D
V
M[15:0]_TXEN
M[15:0]_TXD[1]
Symbol
Zarlink Semiconductor Inc.
Output with pull up
Output with pull up
Output with pull up
Output with pull up
Output with pull up
Output
I/O-TS with pull up
Input
Input with weak
internal pull up
resistors.
Input with weak
internal pull up
resistors
Input with weak
internal pull down
resistors.
I/O- TS with pull up ,
slew
Output, slew
ZL50416
102
I/O
Frame Bank A Write Chip Select for
lower layer of two layers SRAM
configuration
Frame Bank A Write Chip Select for
upper layer of two layers SRAM
configuration
Frame Bank A Read Chip Select for
one bank SRAM configuration
Frame Bank A Read Chip Select for
lower layer of two layers SRAM
configuration
Frame Bank A Read Chip Select for
upper layer of two layers SRAM
configuration
MII Management Data Clock –
(Common for all MII Ports [15:0])
MII Management Data I/O –
(Common for all MII Ports –[15:0]))
Reference Input Clock
Ports [15:0] – Receive Data Bit [1]
Ports [15:0] – Receive Data Bit [0]
Ports [15:0] – Carrier Sense and
Receive Data Valid
Ports [15:0] – Transmit Enable
Strap option for RMII/GPSI
Ports [15:0] – Transmit Data Bit [1]
Description
Data Sheet