zl50416 Zarlink Semiconductor, zl50416 Datasheet - Page 13

• Manufacturer Part Number: zl50416
• Description: Managed 16-port 10/100 M + 2-port 1 G Ethernet Switch
• Manufacturer: Zarlink Semiconductor

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Note that the external MAC table is located in the external SSRAM Memory.
2.0
2.1
Two modes are supported in the ZL50416: managed and unmanaged. In managed mode, the ZL50416 uses an 8
or 16 bit CPU interface very similar to the Industry Standard Architecture (ISA) specification. In unmanaged mode,
the ZL50416 has no CPU but can be configured by EEPROM using an I
synchronous serial interface otherwise.
2.2
In managed mode, the ZL50416 uses an 8 or 16 bit CPU interface very similar to the ISA bus. The ZL50416 CPU
interface provides for easy and effective management of the switching system. Figure 2 provides an overview of the
CPU interface.
INDEX REG 1
(Addr = 001)
SYNCHRONOUS
SERIAL
INTERFACE
Network Management (NM) Database - The NM database contains the information in the statistics counters
and MIB.
MAC address Control Table (MCT) Link Table - The MCT Link Table stores the linked list of MCT entries that
have collisions in the external MAC Table.
Management and Configuration
Managed Mode
System Configuration
16 bit internal
address bus
INDEX REG 0
(Addr = 000)
Figure 2 - Overview of the ZL50416 CPU Interface
8 bit
internal data bus
INTERNAL
CONFIGUE
REGISTERS
Zarlink Semiconductor Inc.
(Addr = 010)
DATA REG
CONFIG
ZL50416
13
RECEIVE
FRAME
FIFO
CPU
FRAME DATA REG
(Addr = 011)
TRANSMIT
8/16 bit internal
data bus
FRAME
FIFO
CPU
2
8/16 bit internal
C interface at bootup, or via a
COMMAND
CONTROL
data bus
RECEIVE
FRAME
FIFO
CONTROL
BLOCK REG
Data Sheet
COMMAND
TRANSMIT
CONTROL
1 AND 2
FRAME
FIFO