zl50416 Zarlink Semiconductor, zl50416 Datasheet - Page 98

• Manufacturer Part Number: zl50416
• Description: Managed 16-port 10/100 M + 2-port 1 G Ethernet Switch
• Manufacturer: Zarlink Semiconductor

Bit[7] - Selects strap option or LCLK/OECLK registers
13.12.7
CPU Address: hF06
Accessed by serial interface (RW)
PD[12:10]
000b
001b
010b
011b
100b
101b
110b
111b
The LCLK delay from SCLK is the sum of the delay programmed in here and the delay in OECLK register.
13.12.8
CPU Address: hF07
Accessed by serial interface (RW)
The OE_CLK is used for generating the OE0 and OE1 signals.
PD[15:13]
000b
001b
010b
011b
100b
101b
110b
111b
13.12.9
CPU Address: hFFF
Accessed by CPU and serial interface (RO)
Always return 8’h DA. Indicate the CPU interface or serial port connection is good.
0 - Strap option (default)
1 - LCLK/OECLK registers
LCLK - LA_CLK delay from internal OE_CLK
OECLK - Internal OE_CLK delay from SCLK
DA – DA Register
OECLK
LCLK
01h
01h
10h
02h
10h
02h
80h
40h
20h
08h
04h
80h
40h
20h
08h
04h
Delay
Delay
1 Buffers Delay
1 Buffers Delay
5 Buffers Delay (Recommend)
2 Buffers Delay
5 Buffers Delay
2 Buffers Delay
8 Buffers Delay
7 Buffers Delay
6 Buffers Delay
4 Buffers Delay
3 Buffers Delay
8 Buffers Delay
7 Buffers Delay (Recommend)
6 Buffers Delay
4 Buffers Delay
3 Buffers Delay
Zarlink Semiconductor Inc.
ZL50416
98
Data Sheet