zl50416 Zarlink Semiconductor, zl50416 Datasheet - Page 3

• Manufacturer Part Number: zl50416
• Description: Managed 16-port 10/100 M + 2-port 1 G Ethernet Switch
• Manufacturer: Zarlink Semiconductor

ZL50416
Data Sheet
Description
The ZL50416 is a high density, low cost, high performance, non-blocking Ethernet switch chip. A single chip
provides 16 ports at 10/100 Mbps, and a CPU interface for managed and unmanaged switch applications.
The chip supports up to 64K MAC addresses and up to 255 port-based Virtual LANs (VLANs). The centralized
shared memory architecture permits a very high performance packet forwarding rate at up to 3.571M packets per
second at full wire speed. The chip is optimized to provide low-cost, high-performance workgroup switching.
The Frame Buffer Memory domains utilize cost-effective, high-performance synchronous SRAM with aggregate
bandwidth of 6.4 Gbps to support full wire speed on all ports simultaneously.
With delay bounded, strict priority, and/or WFQ transmission scheduling, and WRED dropping schemes, the
ZL50416 provides powerful QoS functions for various multimedia and mission-critical applications. The chip
provides 4 transmission priorities and 2 levels of dropping precedence. Each packet is assigned a transmission
priority and dropping precedence based on the VLAN priority field in a VLAN tagged frame, or the DS/TOS field,
and UDP/TCP logical port fields in IP packets. The ZL50416 recognizes a total of 16 UDP/TCP logical ports, 8
hard-wired and 8 programmable (including one programmable range).
The ZL50416 supports 2 groups of port trunking/load sharing. Each 10/100 group can contain up to 4 ports. Port
trunking/load sharing can be used to group ports between interlinked switches to increase the effective network
bandwidth.
In half-duplex mode, all ports support backpressure flow control, to minimize the risk of losing data during long
activity bursts. In full-duplex mode, IEEE 802.3x flow control is provided. The ZL50416 also supports a per-system
option to enable flow control for best effort frames, even on QoS-enabled ports.
Statistical information for SNMP and the Remote Monitoring Management Information Base (RMON MIB) are
collected independently for all ports. Access to these statistical counters/registers is provided via the CPU interface.
SNMP Management frames can be received and transmitted via the CPU interface, creating a complete network
management solution.
The ZL50416 is fabricated using 0.25 micron technology. Inputs, however, are 3.3 V tolerant, and the outputs are
capable of directly interfacing to LVTTL levels. The ZL50416 is packaged in a 553-pin Ball Grid Array package.
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Zarlink Semiconductor Inc.