zl50416 Zarlink Semiconductor, zl50416 Datasheet - Page 91

• Manufacturer Part Number: zl50416
• Description: Managed 16-port 10/100 M + 2-port 1 G Ethernet Switch
• Manufacturer: Zarlink Semiconductor

13.10.3
I
Accessed by CPU, serial interface and I
2
C Address F2, CPU Address:h602)
Bits [0]:
Bits[1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]:
FEN – Feature Register
7
DML
Mii
6
Statistic Counter Enable (Default 0)
When statistic counter is enable, an interrupt control frame is generated to
the CPU, every time a counter wraps around. This feature requires an
external CPU.
Rate Control Enable (Default 0)
This bit enables/disables the rate control for all 10/100 ports. To start rate
control in a 10/100 port the rate control memory must be programmed. This
feature requires an external CPU. See Programming QoS Registers
application note and Processor Interface application note for more
information.
Support DS EF Code. (Default 0)
When 101110 is detected in DS field (TOS[7:2]), the frame priority is set for
110 and drop is set for 0.
Enable VLAN spanning tree support (Default 0)
When VLAN spanning tree is enable the registers ECR1Pn are NOT used to
program the port spanning tree status. The port status is programmed using
the Control Command Frame.
Disable IP Multicast Support (Default 1)
When enable, IGMP packets are identified by search engine and are passed
to the CPU for processing. IP multicast packets are forwarded to the IP
multicast group members according to the VLAN port mapping table.
Enable report to CPU(Default 0)
When disable new VLAN port association report, new MAC address report or
aging reports are disable for all ports. When enable, register SE_OPEMODE
is used to enable/disable selectively each function.
Disable MII Management State Machine (Default 0)
Rp
- 0 – Disable
- 1 – Enable (all ports)
- 0 – Disable
- 1 – Enable
- 0 – Disable
- 1 – Enable (all ports)
- 0 – Disable
- 1 – Enable
- 0 – Enable IP Multicast Support
- 1 – Disable IP Multicast Support
- 0 – Disable report to CPU
- 1 – Enable report to CPU
- 0: Enable MII Management State Machine
- 1: Disable MII Management State Machine
5
IP Mul
4
2
C (R/W)
V-Sp
Zarlink Semiconductor Inc.
3
ZL50416
DS
2
91
RC
1
0
SC
Data Sheet