zl50416 Zarlink Semiconductor, zl50416 Datasheet - Page 72

• Manufacturer Part Number: zl50416
• Description: Managed 16-port 10/100 M + 2-port 1 G Ethernet Switch
• Manufacturer: Zarlink Semiconductor

Bit[3]: Select Queue 3
Note: Strip priority applies between different selected queues (Q3>Q2>Q1>Q0)
Bit[4]: Enable flush Queue 0
Bit[5]: Enable flush Queue 1
Bit[6]: Enable flush Queue 2
Bit[7]: Enable flush Queue 3
When flush (drop frames) is enable, it starts when queue is too long or entry is too old. A queue is too long when it
reaches WRED thresholds. Queue 0 is not subject to early drop. Packets in queue 0 are dropped only when the
queue is too old. An entry is too old when it is older than the time programmed in the register TX_AGE [5:0]. CPU
can dynamically program this register reading register RQSS [7:4].
13.7.17
CPU Address:h324
Accessed by CPU, serial interface (RO)
CPU receive queue status
13.7.18
I
Accessed by CPU, serial interface (RW)
Disable transmission queue aging if value is zero. Aging timer for all ports and queues.
This register must be set to 0 for ‘No Packet Loss Flow Control Test’.
13.8
13.8.1
I
Accessed by CPU, serial interface and I
The ZL50416 removes the MAC address from the data base and sends a Delete MAC Address Control Command
to the CPU. MAC address aging is enable/disable by boot strap TSTOUT9.
Bit [7:0] Low byte of the MAC address aging timer.
2
2
C Address: h07;CPU Address:h324
C Address h0A8; CPU Address:h400
- Bit[3:0]: Queue 3 to 0 not empty
- Bit[4]: Head of line entry for Queue 0 is valid for too long. CPU Queue 0 has no WRED threshold.
- Bit[7:5]: Head of line entry for Queue 3 to 1 is valid for too long or Queue length is longer than WRED threshold.
- Bit[5:0]: Unit of 100ms (Default 8)
(Group 4 Address) Search Engine Group
AGETIME_LOW – MAC address aging time Low
RQSS – Receive Queue Status
TX_AGE – Tx Queue Aging timer
7
LQ3
7
LQ2
6
LQ1
5
Tx Queue Agent
5
4
LQ0
2
C (R/W)
Zarlink Semiconductor Inc.
3
NeQ3
ZL50416
72
NeQ2
NeQ1
0
0
NeQ0
Data Sheet