zl50416 Zarlink Semiconductor, zl50416 Datasheet - Page 33

• Manufacturer Part Number: zl50416
• Description: Managed 16-port 10/100 M + 2-port 1 G Ethernet Switch
• Manufacturer: Zarlink Semiconductor

Px is the total byte count, in the priority queue x. The WRED logic has three drop levels, depending on the value of
N, which is based on the number of bytes in the priority queues. If delay bound scheduling is used, N equals
P3*16+P2*4+P1. If using WFQ scheduling, N equals P3+P2+P1. Each drop level from one to three has defined
high-drop and low-drop percentages, which indicate the minimum and maximum percentages of the data that can
be discarded. The X, Y Z percent can be programmed by the register RDRC0, RDRC1. In Level 3, all packets are
dropped if the bytes in each priority queue exceed the threshold. Parameters A, B, C are the byte count thresholds
for each priority queue. They can be programmed by the QOS control register (refer to the register group 5). See
Programming QoS Registers application note for more information.
7.8
Because the number of FDB slots is a scarce resource, and because we want to ensure that one misbehaving
source port or class cannot harm the performance of a well-behaved source port or class, we introduce the concept
of buffer management into the ZL50416. Our buffer management scheme is designed to divide the total buffer
space into numerous reserved regions and one shared pool, as shown in Figure 12.
As shown in the figure, the FDB pool is divided into several parts. A reserved region for temporary frames stores
frames prior to receiving a switch response. Such a temporary region is necessary, because when the frame first
enters the ZL50416, its destination port and class are as yet unknown, and so the decision to drop or not needs to
be temporarily postponed. This ensures that every frame can be received first before subjecting them to the frame
drop discipline after classifying.
Six reserved sections, one for each of the first six priority classes, ensure a programmable number of FDB slots per
class. The lowest two classes do not receive any buffer reservation. Furthermore, even for 10/100 Mbps ports, a
frame is stored in the region of the FDB corresponding to its class. As we have indicated, the eight classes use only
four transmission scheduling queues for 10/100 Mbps ports, but as far as buffer usage is concerned, there are still
eight distinguishable classes.
Another segment of the FDB reserves space for each of the 17 regions — 16 ports for Ethernet and one CPU port
(port number 24). One parameters can be set, one for the source port reservation for 10/100 Mbps ports and CPU
port. These 17 reserved regions make sure that no well-behaved source port can be blocked by another
misbehaving source port.
In addition, there is a shared pool, which can store any type of frame. The frame engine allocates the frames first in
the six priority sections. When the priority section is full or the packet has priority 1 or 0, the frame is allocated in the
shared poll. Once the shared poll is full the frames are allocated in the section reserved for the source port.
The following registers define the size of each section of the Frame data Buffer:
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PR100- Port Reservation for 10/100 Ports
SFCB- Share FCB Size
C2RS- Class 2 Reserve Size
C3RS- Class 3 Reserve Size
C4RS- Class 4 Reserve Size
C5RS- Class 5 Reserve Size
C6RS- Class 6 Reserve Size
C7RS- Class 7 Reserve Size
Buffer Management
Zarlink Semiconductor Inc.
ZL50416
33
Data Sheet