zl50416 Zarlink Semiconductor, zl50416 Datasheet - Page 86

• Manufacturer Part Number: zl50416
• Description: Managed 16-port 10/100 M + 2-port 1 G Ethernet Switch
• Manufacturer: Zarlink Semiconductor

13.9.33.1
USER_PORT_0 - I
USER_PORT_1 - I
USER_PORT_2 - I
USER_PORT_3 - I
USER_PORT_4 - I
USER_PORT_5 - I
USER_PORT_6 - I
USER_PORT_7 - I
Accessed by CPU, serial interface and I
(Default 00) This register is duplicated eight times from PORT 0 through PORT 7 and allows the CPU to define
eight separate ports.
13.9.33.2
I
Accessed by CPU, serial interface and I
The chip allows the CPU to define the priority
13.9.33.3
I
Accessed by CPU, serial interface and I
2
2
C Address h0E6, CPU Address 590
C Address h0E7, CPU Address 591
Bits[3:0]:
Bits[7:4]:
USER_PORT0_(0~7) – User Define Logical Port (0~7)
USER_PORT_[1:0]_PRIORITY - User Define Logic Port 1 and 0 Priority
USER_PORT_[3:2]_PRIORITY - User Define Logic Port 3 and 2 Priority
7
TCP/UDP Logic Port Low
7
TCP/UDP Logic Port High
7
Priority 1
7
Priority 3
2
2
2
2
2
2
2
2
C Address h0D6 + 0DE; CPU Address 580(Low) + 581(high)
C Address h0D7 + 0DF; CPU Address 582 + 583
C Address h0D8 + 0E0; CPU Address 584 + 585
C Address h0D9 + 0E1; CPU Address 586 + 587
C Address h0DA + 0E2; CPU Address 588 + 589
C Address h0DB + 0E3; CPU Address 58A + 58B
C Address h0DC + 0E4; CPU Address 58C + 58D
C Address h0DD + 0E5; CPU Address 58E + 58F
Priority setting, transmission + dropping, for logic port 0
Priority setting, transmission + dropping, for logic port 1 (Default 00)
5
5
4
Drop
4
Drop
2
2
2
3
Priority 0
C (R/W)
C (R/W)
C (R/W)
3
Priority 2
Zarlink Semiconductor Inc.
ZL50416
1
1
86
Drop
Drop
0
0
0
0
Data Sheet